应变Si调制掺杂NMOSFET电子面密度模型

应变Si(Strain Si)调制掺杂NMOSFET量子阱沟道中电子面密度直接影响器件的开关特性.本文通过求解泊松方程,建立了应变Si调制掺杂NMOSFET量子阱沟道静态电子面密度模型,并据此建立了器件阈值电压模型,利用MATLAB软件对该模型进行了数值分析.讨论了器件结构中δ-掺杂层杂质浓度和间隔层厚度与电子面密度和阈值电压的关系,分析了器件几何结构参数和材料物理参数对器件量子阱沟道静态电子面密度和阈值电压的影响.随着δ-掺杂层杂质浓度的减小和间隔层厚度的增加,量子阱沟道中电子面密度减小,阈值电压绝对值减小.     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

MOSFET衬底电流模型在深亚微米尺寸下的修正

建立精确的衬底电流模型是分析MOSFET器件及电路可靠性和进行MOSFET电路设计所必需的.在分析载流子输运的基础上建立了一个常规结构深亚微米MOSFET衬底电流的解析模型,模型公式简单.对模型进行了验证,研究了衬底掺杂浓度与栅氧化层厚度对拟合因子的影响,并分析了模型中拟合因子的物理意义.     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。     

热载流子注入对器件性能影响及其改善措施

当载流子在大于10~4V·cm~(-1)的电场下运动时,它从电场获得的能量大于散射过程中与晶格原子碰撞损失的能量,因而载流子的温度将会超过晶格温度.这样的载流子就称为热载流子.在VLSIC中,为了达到高速度和高集成度,设计时必须采用一系列的折衷方案.为了避免短沟道效应,增加了体掺杂浓度,以使较小的沟道长度的器件保证质量,获得小的亚阈值泄漏电流.由于驱动电流的降低,栅氧化层厚度也按比例缩小.减小沟道长度、减薄氧化层厚度以及相应增加了体掺杂浓度,这些综合结果有助于产生和注入热载流子.一旦晶体管表面反     

pMOS器件NBTI效应随着器件参数变化规律的一种模型

器件的负偏压温度不稳定性(Negative bias temperature instability,NBTI)退化依赖于栅氧化层中电场的大小和强反型时沟道空穴浓度,沟道掺杂浓度的不同显然会引起栅氧化层电场的变化。栅氧化层的厚度不仅影响栅氧化层电场,而且会影响沟道空穴浓度,因而,改变沟道掺杂浓度和栅氧化层厚度会引起NBTI退化的不同。首先利用pMOSFETS器件的能带图和NBTI的退化模型,推导出了器件NBTI随器件参数变化的公式,并修订了NBTI的数值模拟方法,然后分别利用理论计算和数值模拟的方法对不同器件参数、相同阈值电压的器件进行定量地计算和仿真,继而总结出一种分析器件NBTI退化的应用模型,可对集成电路和器件的可靠性设计提供指导。     

一种新的Halo掺杂圆柱围栅MOSFET阈值电压解析模型

通过在圆柱坐标系中精确求解泊松方程,建立了全新的Halo掺杂圆柱围栅MOSFET静电势,电场以及阈值电压的解析模型。与采用抛物线电势近似法得到的解析模型相比,当沟道半径远大于氧化层厚度时,新模型更为精确。模型还考虑了Halo区掺杂浓度、氧化层厚度以及沟道半径对器件阈值电压特性的影响。结果表明,采用中等程度的halo区掺杂浓度、较薄的栅氧化层以及较小的沟道半径可以有效改善器件的阈值电压特性。解析模型与三维数值模拟软件ISE所得结果高度吻合。     

基于神经网络的纳米MOSFET反型层载流子密度量子更正

文章提出了基于Levenberg—Marquardt BP神经网络的MOSFET反型层载流子密度量子更正模型．对于较大氧化层厚度范围、Si层厚度范围、栅压范围和掺杂浓度范围的单栅以及双MOSFET．Si反型层备点的载流子量子密度都可以通过经典载流子密度进行快速预测，预测结果与Schrodinger—Poisson程的平均相对误差不超过5％。     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

GeSi-PMODMOS器件研究

在分析PMODMOS结构以及器件物理基础上,重点研究了GeSi沟道中Ge含量分布、超薄栅介质层SiO2和Si帽层厚度等对GeSi－PMODMOS特性的影响。介绍了与GeSi-PMODMOS结构器件相关的超薄栅介质层（PESiO2,LPSiO2）、超浅结工艺和超浅结金属化等重要工艺技术。     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

一种积累型槽栅超势垒二极管

提出了一种积累型槽栅超势垒二极管,该二极管采用N型积累型MOSFET,通过MOSFET的体效应作用降低二极管势垒。当外加很小的正向电压时,在N+区下方以及栅氧化层和N-区界面处形成电子积累的薄层,形成电子电流,进一步降低二极管正向压降;随着外加电压增大,P+区、N-外延区和N+衬底构成的PIN二极管开启,提供大电流。反向阻断时,MOSFET截止,PN结快速耗尽,利用反偏PN结来承担反向耐压。N型积累型MOSFET沟道长度由N+区和N外延区间的N-区长度决定。仿真结果表明,在相同外延层厚度和浓度下,该结构器件的开启电压约为0.23 V,远低于普通PIN二极管的开启电压,较肖特基二极管的开启电压降低约30%,泄漏电流比肖特基二极管小近50倍。     

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N⁺ polysilicon gate device with highly doped Si layer, an asymmetrical P⁺/N⁺ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P⁺/N⁺ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.     

Influences of /spl delta/-doping position on the characteristics of SiGe-Si DCFETs

SiGe-Si doped channel field-effect-transistors with different positions of /spl delta/ layers in SiGe wells have been proposed and fabricated. High forward gate to drain turn-on voltage (>0.87 V) and reverse breakdown voltage up to 25 V was obtained for center and bottom /spl delta/-doped channel devices. For device structures with the same 1/spl times/100 /spl mu/m/sup 2/ gate, center /spl delta/-doped channel device display the best dc maximum extrinsic transconductance of 22.1 mS/mm. Compared with conventional Si-SiGe MODFETs, center /spl delta/-doped channel device exhibits improved gate voltage swings as wide as 3 V due to the better carrier confinement and the absence of parallel conduction, which is promising to provide an additional degree of freedom for Si-based device applications.     

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structuresfor high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V_th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V_th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

Simulation study on comparison between metal gate and polysilicongate for sub-quarter-micron MOSFETs

Two-dimensional (2-D) process and device simulation is used to investigate the effectiveness of the depletion-free metal gate for a sub-quarter-micron MOSFET as compared with surface channel polysilicon gate MOSFETs which suffer greatly from the gate depletion effect. The results reveal that the subthreshold characteristic for the metal gate NMOSFET is considerably degraded since the depletion-free merit is covered up by an undesirable influence of the buried channel structure, which is indispensable to obtain an appropriate threshold voltage for the midgap gate. Consequently, the drivability of the metal gate MOSFET is comparable to that of the heavily doped polysilicon gate MOSFET under commonly used conditions, and further, the metal gate structure is disadvantaged against the reduction of the supply voltage     

Si（Ge）MOSFET器件微结构的研究

采用横断面的透射电子显微术，扫描电子显微术和高分辨电子显微学方法，研究了ＧｅＳｉ沟道ｐ－ＭＯＳＦＥＴ的微结构。观察表明，器件是由Ｓｉ基片／ＳｉＯ２非晶层／ＳＯＩＳｉ层／ＧｅＳｉ沟道层／超薄ＳｉＯ２非晶层／Ｓｉ细晶层／ＳｉＯ２非晶层／Ａｌ电极层等组成的；ＳＯＩＳｉ层工作区单晶性良好，很难找到缺陷，缺陷能效地被限制在工作两侧的缺陷聚集区；在ＳＯＳＳｉ层和ＧｅＳｉ沟道层之间存在着一些瓣状衬底，它可能是在