前馈式RF功率放大器的线性化技术

针对现代高频通信的要求,介绍了一种含导频信号的前馈式RF功率放大器的线性化技术,并详尽论述了其工作原理。     

导频前馈功率放大器线性化技术的研究

为了使前馈功放具有自适应能力,设计了一种基于单片机实现的导频前馈功放.分析了导频前馈功放的工作原理,在此基础上阐述了导频自适应调整的过程,并对可调移相器、可调衰减器的位置进行了讨论.最后介绍了单片机和接口芯片的连接和运行过程.该导频前馈功放不仅具有很高的线性度,而且还具有了自适应能力.     

基于导频检测技术的射频前馈功放研究

介绍了基于导频检测技术的前馈射频功放线性化技术,从理论上简单地分析了前馈功放以及利用导频信号自适应控制前馈功放的原理.利用导频法控制前馈有很多地电路结构,包括导频跳频、导频信号扩展和导频调制.导频法检测技术是一种简单而有效的控制技术,该技术的关键是选择合适的导频信号频率和信号的大小.通过对选定的最新的元器件,采用典型的导频前馈法用ADS进行仿真,并给出仿真结果,然后提出一个实际有效的导频法线性化方案.     

射频功率放大器的线性化技术

本文阐述了射频功率放大器非线性产生的原因，介绍了几种射频功放的线性化技术，以便于射频功放设计者参考。     

前馈自适应射频功率放大器线性技术研究

介绍一种用于改善射频功率放大器非线性失真的前馈技术,并基于前馈系统,增加了自适应控制电路,提出使输出的交调信号功率最小化的方法来分别控制两个支路上的相位和幅度调节器,使系统性能稳定：本文较详尽地讨论了系统工作原理,通过ADS软件仿真．结果表明能显著改善IMD性能。     

自适应前馈射频功率放大器设计

在高功率射频放大器设计时，通常采用前馈技术来改善宽带信号的线性度。本文基于普通的前馈系统。提出了一种新的自适应前馈线性化技术，并结合信号包络检测技术进行带外信号调节。同时，还利用该技术在计算机仿真系统上设计了一个射频功率放大器的功放输出级，通过对仿真结果的比较，发现他能显著改善IMD性能。     

射频功率放大器线性化技术研究

在当今社会,随着无线通信技术的发展和应用,人们开始追求高功率效率和高频谱利用率。基于此,高效射频功率放大器、线性调制技术等,都开始得到越来越广泛的应用。但是,经过非线性射频功率放大的包络变化调制信号,时常会产生互调失真的情况,会引发较为严重的临近信道干扰以及码间干扰等问题。对此,在对射频功率放大器进行应用的过程中,应当注重采用线性化技术,以确保良好的通信质量。     

前馈功率放大器的仿真设计

首先讨论了功率放大器前馈线性化方法的基本原理,并用HPADS对一个真实的线性功率放大器进行仿真设计试验,结果表明基本系统对三阶交调有很好的抑制作用.针对此类功率放大器的不足,探讨了一种改进措施,给出了设计原理图,有望在不增加系统复杂性的基础上,显著提高前馈法的效率.     

射频功率放大器的线性化技术

本文阐述了射频功率放大器非线性产生的原因,介绍了几种射频功放的线性化技术,以便于射频功放设计者参考。     

基于射频功率放大器线性化技术研究

在现如今社会中,无线通信技术正在快速发展及完善,人们在实际应用中对于无线通信技术的功率及利用率也提出了更加严苛的要求.所以,高效率射频功能放大器等等技术开始逐渐被人们应用,但是这个技术在实际应用过程中,会经常出现互调失真的问题,对于信号通道进行干扰.所以,射频功率放大器在实际应用过程中,应该提高对其线性技术的有关研究,进而保证通信质量.     

一种改善W-CDMA手机用功率放大器线性度的新方法

分析了偶次交调产生的低频因素对临近信道泄漏功率比(ACPR)不对称性的影响;根据实际功率放大器结构提出了一种等效低通滤波器模型;仿真验证了该低通滤波器的带宽和阶数对ACPR不对称性的影响;测试中通过改变该低通滤波器的带宽和阶数,使得ACPR不对称性改善了3.72dB,同时ACPR降低了2.95dB,有效地改善了功率放大器的线性度。     

宽带增益平坦光纤Raman放大器的研究进展

宽带增益平坦光放大器是密集波分复用光通信系统提高信息容量的基本需求。在总结宽带掺铒光纤放大器的基础上 ,介绍了展宽光纤Raman放大器平坦增益带宽的基本方法和研究现状。     

A Low‐Voltage High‐Performance CMOS Feedforward AGC Circuit for Wideband Wireless Receivers

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling‐time constraints. This makes the use of traditional closed‐loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast‐settling response. The AGC has been implemented in a 0.35 μm standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 μs.     

线性光放大器的宽带自发辐射噪声分析

建立含有垂直光场(VCL)的线性光放大器(LOAs)稳态仿真模型,考虑了宽带噪声特性、端面反射和纵向空间烧孔效应。计算了在不同输入信号功率和垂直腔分布布喇格反射器(DBR)反射率下总的输出ASE噪声功率、噪声系数(NF)、前向和后向传输的ASE噪声光子速率和噪声谱分布的变化。结果表明,与传统光放大器(SOAs)相比,在增益非饱和区,LOA有很好的噪声钳制作用,ASE噪声几乎不随信号功率的改变而变化。在增益饱和区,破坏了VCL的钳制作用,NF有所上升,但上升的速率小于SOA。提高DBR反射率,总的输出ASE噪声功率减小,但NF有所增大。     

Improving the Graceful-Degradation Performance of Combined Power Amplifiers

The standard method of employing n-way hybrid power divider/combiner to combine n amplifiers offers some sort of graceful-degradation performance when one or more of the amplifiers fail. Two schemes are discussed that improve that performance significantly. The first, which was proposed previously, involves replacing each failed amplifier by an equal-delay "through" connection. The second involves using a resistor-free combiner, and seperating each failed amplifier from the combiner by an appropriately placed short or open circuit.     

Architectural Modifications to Enhance the Floating-Point Performance of FPGAs

With the density of field-programmable gate arrays (FPGAs) steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpose nature has limited the use of FPGAs in scientific applications that require floating-point arithmetic due to the large amount of FPGA resources that floating-point operations still require. This paper considers three architectural modifications that make floating-point operations more efficient on FPGAs. The first modification embeds floating-point multiply-add units in an island-style FPGA. While offering a dramatic reduction in area and improvement in clock rate, these embedded units are a significant change and may not be justified by the market. The next two modifications target a major component of IEEE compliant floating-point computations: variable length shifters. The first alternative to lookup tables (LUTs) for implementing the variable length shifters is a coarse-grained approach: embedded variable length shifters in the FPGA fabric. These shifters offer a significant reduction in area with a modest increase in clock rate and are smaller and more general than embedded floating-point units. The next alternative is a fine-grained approach: adding a 4:1 multiplexer unit inside a configurable logic block (CLB), in parallel to each 4-LUT. While this offers the smallest overall area improvement, it does offer a significant improvement in clock rate with only a trivial increase in the size of the CLB.     

Simulation Performance of Erbium-Doped Fiber Amplifiers

In this paper, a simple approach is introduced to simulate the main performance of erbium-doped fiber amplifiers by using two empirical formulas to calculate saturated gain and corresponding noise figure. Then conflict equations are presented to improve this approach. At the end of the paper the comparison of calculation results before and after improvement is given. It has been shown to be more accurate.     

有关L波段EDFA的模型及其解法

通过Giles C R的EDFA数学模型，经过一系列的变换和近似得到一组光场强度与)曼转离子数浓度之间的带边界条件的偏微分方程。我们通过特定的数值方法解此方程组得到L波段EDFA的相关特性。     

有关L波段EDFA的模型及其解法

通过Giles C R的EDFA数学模型,经过一系列的变换和近似得到一组光场强度与反转离子数浓度之间的带边界条件的偏微分方程。我们通过特定的数值方法解此方程组得到L波段EDFA的相关特性。