Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

一种CMOS工艺离子敏场效应型晶体管的模型

采用CMOS工艺可以实现离子敏场效应型晶体管(ISFET),若在栅极氧化层之上保留多晶硅层,并通过引线使其与 外界的金属层相连作为悬浮的栅极,可实现悬浮栅结构ISFET.从ISFET的传感机理出发,根据表面基模型,利用HSPICE建 立了悬浮栅结构ISFET的物理模型.以该模型为研究对象,探讨了薄膜等效电阻、薄膜等效电...     

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

新型低Cgs射频LDMOS器件设计

为了降低栅源寄生电容Cgs,提出了一种带有阶梯栅n埋层结构的新型射频LDMOS器件;采用Tsuprem4软件对其进行仿真分析,重点研究了n埋层掺杂剂量和第二阶梯栅氧厚度对栅源寄生电容Cgs的影响,并结合传统的射频LDMOS基本结构对其进行优化设计。结果表明：这种新型结构与传统的射频LDMOS器件结构相比,使得器件的栅源寄生电容最大值降低了15.8%,截止频率提高了7.6%,且器件的阈值电压和击穿电压可以维持不变。     

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-/spl kappa/ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.     

Parasitic capacitance removal of sub-100 nm p-MOSFETs using capacitance–voltage measurements

Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.     

功率VDMOS器件的ESD瞬态模型

基于对功率VDMOS器件ESD保护及初始条件的分析,建立了VDMOS器件的ESD保护等效电路,分析了ESD响应过程,得到功率VDMOS器件的ESD瞬态模型. 分析结果表明,该模型准确地描述了功率VDMOS器件的ESD瞬态放电过程,解决了以往模型中初始条件分析不足等问题. 借助该模型,获得ESD器件的等效电阻和击穿电压、VDMOS的栅极输入电阻、栅源电容、栅氧厚度等与功率VDMOS器件抗ESD能力的关系,为功率VDMOS器件的抗ESD保护设计提供重要指导.     

A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Quasi-saturation capacitance behavior of a DMOS device

This paper reports a simulation study on the capacitance characteristics of a double-diffused metal-oxide semiconductor (DMOS) device operating in the quasi-saturation region. From the analysis, the capacitance effect of the gate oxide upon the drift region cannot be modeled as an overlap capacitance, because the drain-gate/source-gate capacitances of the DMOS device may exceed the gate-oxide capacitance due to the larger voltage drop over the gate oxide than the change in the imposed gate bias when entering the quasi-saturation region. This effect can be the explanation for the plateau behavior in the gate charge plot during turn-on and turn-off of the DMOS device. Based on the small-signal equivalent capacitance model, the accumulated charge in the drift region below the gate oxide may thoroughly associate with the drain terminal in the prequasi-saturation region and with the source terminal in the quasi-saturation region     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

GaAs ultra-high-frequency dividers with advanced SAINT FET's

The circuit design, fabrication, and performance of ultra-high-frequency dividers with buffer FET logic (BFL) circuits are described. Using air-bridge technology and a new, self-aligned-gate, GaAs FET process, called advanced SAINT, which avoids excess gate metal overlap on the dielectric film, 10.6-GHz operation at 258 mW is achieved. This performance is made possible by a reduction of gate and interconnection parasitic capacitance. Furthermore, the possibility of operation above 20 GHz for GaAs MESFET frequency dividers is predicted on the basis of circuit optimization and FET improvements including parasitic capacitance reduction and transconductance enhancement.     

Determination of mobility in modulation-doped FET's using magnetoresistance effect

A simple measurement technique based on the magnetoresistance effect is developed to obtain the differential and average mobilities of modulation-doped field-effect transistors (MODFET's) with respect to gate bias voltage. The effect of parasitic series resistances can be neglected by using a low magnetic field. The measurement is not affected by parasitic gate capacitance and therefore constitutes an effective tool for characterizing fully processed ultra-short gate-length MODFET's.     

Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs

The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail. By careful design, the short channel short channel effects can be suppressed by the elevated source/drain (S/D) structure. In addition, the S/D region parasitic capacitance is significantly suppressed by the silicon-on-insulator (SOI)-like S/D structure. Tradeoff between series resistance and gate-to-drain Miller capacitance can be achieved by carefully selecting the gate spacer thickness. With careful optimization of device geometry, both the gate-delay and power consumption can be significantly reduced together. Design guideline and potential performance gain with the S/D-on-insulator structure is discussed.     

Extremely low-noise performance of GaAs MESFETs with wide-headT-shaped gate

Fully ion-implanted low-noise GaAs MESFETs with a 0.11-μm Au/WSiN T-shaped gate have been successfully developed for applications in monolithic microwave and millimeter-wave integrated circuits (MMICs). In order to reduce the gate resistance, a wide Au gate head made of a first-level interconnect is employed. As the wide gate head results in parasitic capacitance, the relation between the gate head length (L_h) and the device performance is examined. The gate resistance is also precisely calculated using the cold FET technique and Mahon and Anhold's method. A current gain cutoff frequency (f_T) and a maximum stable gain (MSG) decrease monotonously as L_h increases on account of parasitic capacitance. However, the device with L_h of 1.0 μm, which has lower gate resistance than 1.0 Ω, exhibits a noise figure of 0.78 dB with an associated gain of 8.7 dB at an operating frequency of 26 GHz. The measured noise figure is comparable to that of GaAs-based HEMT's