Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Ultra-Fine Pitch Stencil Printing for a Low Cost and Low Temperature Flip-Chip Assembly Process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process     

Development of a mathematical model for thermal-compression bonding of the COG packaging process using NCA

In this decade, many new techniques have been introduced into the integrated circuit (IC) packaging industry. Packaging technology used in liquid crystal displays (LCDs) has requirements related to critical issues such as high density interconnects, thinner packaging size, and environmental safety. Driver IC chips are directly attached to LCD panels using flip chip technology with adhesives in the so called chip on glass (COG) packaging processes. To investigate the dependence of the bonding force on the bump deformation during packaging, this study established a mathematical model to analyze COG packaging processes with non-conductive adhesives (NCAs). The plastic deformation of the bumps and the NCA flow between the chip and substrate are taken into account in this model. With this model, the contact resistance and the gap height after bonding can be estimated for different bonding force.     

应用于平板显示器封装的ACF新进展

随着平板显示器大型化、薄型化、高分辨率的发展趋势,对平板显示器封装技术提出了更高的要求.ACF符合电子线路封装精细化、集成化的发展要求,目前已广泛应用于平板显示器(例如LCD)的封装领域.综述了ACF应用于平板显示器封装的主要形式如TCP、COF、COG,分析了各种不同封装形式对ACF提出的不同性能要求,以及为了满足这些要求对ACF中导电粒子的大小、含量、硬度以及ACF中使用树脂的种类等方面进行结构性能改进的最新进展.     

Physical design issues for very large ATM switching systems

The authors examine the physical design issues associated with terabit/second switching systems, particularly with regard to the customer access portion of the switch. They determine the physical design requirements in the areas of backplane interconnections, integrated circuit packaging, and circuit board technology and identify areas where existing- or near-future physical design technologies are inadequate to meet the requirements of this application. A new 3D interconnection architecture that solves some of the problems encountered at the backplane level is suggested. It is also suggested that multichip module technology will help meet some of the speed and density requirements at the chip packaging level. Some of the system-level consequences of the proposed model are discussed     

Metal–Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging

The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 mum). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80deg. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45degC. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging.     

/spl beta/-Helix: a lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed /spl beta/-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the /spl beta/-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. /spl beta/-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed /spl beta/-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of /spl beta/-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant /spl beta/-Helix interconnect will have a total standoff height of 110 /spl mu/m, radius of 37 /spl mu/m and cross section area of 525 /spl mu/m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the /spl beta/-Helix interconnect, especially when the interconnect density is high.     

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

This paper reports the design, assembly and reliability assessment of 21 × 21 mm² Cu/low-k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.By integrating PEDL to the Cu/low-k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low-k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low-k generations.     

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Facing the challenge of designing for Cu/low-k reliability

With the decrease of the feature size to 90 nm and lower new materials are introduced in the waferfabs. Copper replaced aluminium and low-k dielectrics served as a better isolator. But this change has serious consequences for the structural integrity of the IC interconnects after processing and package manufacturing. Due to the fact that the new materials have substantially different thermo-mechanical properties, sufficient reliability performance for the IC package becomes a key factor. This paper presents solutions for the reliability problems faced due to the introduction of Cu/low-k as a consequence of the packaging processes. The packaging processes that significantly endanger the Cu/low-k integrity are probing, wire bonding, and moulding. Examples of the reliability issues are presented; these are deep probe marks, metal peel off, and/or pulled-off IC layers. To solve these issues, packaging process conditions and material properties are tuned to better fit with the Cu/low-k technology. Hopefully, the lessons learned and the newly developed state-of-the-art modelling and experimental techniques will enable the industry to release the lower node technologies such as CMOS065.     

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.     

Characterization and modeling of static and cyclic relaxation in nonconductive adhesives

Adhesive interconnections are considered to be attractive alternatives to lead or lead-free solder interconnects because of their lower processing temperatures and extendability to fine pitch applications. However, reliability issues, such as moisture-induced delamination and viscoelastic relaxation of the adhesive in both steady-state and cyclic loading, continue to pose a challenge to widespread implementation. To date, the static and cyclic relaxation characteristics of nonconductive adhesives (NCAs) are yet to be understood. This paper attempts to provide insights into this static and cyclic relaxation behavior through experimental characterization and modeling. The viscoelastic property of a typical NCA material was characterized, and a simulation program with integrated circuit emphasis (SPICE) modeling program was used to model the cyclic relaxation behavior. The modeling results were successfully validated with a series of experiments. This showed that cyclic relaxation of the adhesive can be successfully modeled using linear-viscoelastic property. The phenomenon of slower relaxation of the adhesive under cyclic loading than that in static loading suggests that accelerated reliability testing used in solder-joint fatigue durability investigations may not be directly applicable to the adhesive interconnections. A rework methodology applicable to adhesive interconnects using cyclic loading has also been proposed.     

芯片制造的电化学处理技术

电化学处理技术的性价比优势在芯片制造上是一个范例转移。Cu芯片金属化的双大马士革处理和面阵列芯片封装互连的C4(倒装)技术使电化学技术置于最复杂的制造工艺技术之间。这些工艺技术被集成到用于芯片制造的300mm晶圆处理中。新材料和工艺的持续发展来满足微处理器件不断增加性能和小型化的趋势。电迁移问题和集成超低k电介质材料与Cu镀层的新抛光方法是芯片制造中的一个关键问题。发展一个适用成本低的无铅C4芯片封装互连是微电子工业的主要目标,微电子工业正作努力在几年里市场化无铅产品。     

基于埋置式基板的3D-MCM封装结构的研制

研制一种用于无线传感网的多芯片组件（3D-MCM) . 采用层压、开槽等工艺获得埋置式高密度多层有机（FR-4）基板,通过板上芯片（COB) 、板上倒装芯片（FCOB) 、球栅阵列（BGA）等技术,并通过引线键合、倒装焊等多种互连方式将不同类型的半导体芯片三维封装于一种由叠层模块所形成的立体封装结构中;通过封装表层的植球工艺形成与表面组装技术（SMT）兼容的BGA器件输出端子;利用不同熔点焊球实现了工艺兼容的封装体内各级BGA的垂直互连,形成了融合多种互连方式3D-MCM封装结构. 埋置式基板的应用解决了BGA与引线键合芯片同面组装情况下芯片封装面高出焊球高度的关键问题. 对封装结构的散热特性进行了数值模拟和测试,结果表明组件具有高的热机械可靠性. 电学测试结果表明组件实现了电功能,从而满足了无线传感网小型化、高可靠性和低成本的设计要求.     

Stable Electrical Operation of 6H–SiC JFETs and ICs for Thousands of Hours at 500 $^{circ}hbox{C}$

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500degC in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high-temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500degC operational testing. These results establish a new technology foundation for realizing durable 500degC ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.     

Fatigue analysis of high-speed photodiode submodule by using FEM

Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density.     

Transition of MCM-C applications to MCM-L using rigid flex substrates

Rigid flex circuits have historically been used in military and high-end performance electronic packaging to improve reliability, reduce weight and save space. This type of interconnect offers higher reliability and a tighter form factor when compared to more conventional interconnect techniques. Improvements in printed circuit fabrication processes and laminate materials have made possible unique opportunities for high density rigid flex circuitry. Recently MCM-L or laminate based multi chip modules have been gaining in popularity as a lower cost packaging alternative to traditional MCM-C or ceramic substrate based multi chip modules. This paper describes the steps taken to redesign existing modules from MCM-C technology to MCM-L(F). Several actual products that have been redesigned from ceramic substrate technology to laminate based packaging using rigid flex as the enabling technology are shown. Data is presented on thermal dissipation, mechanical reliability, electrical performance, and thermal reliability of the laminate substrate as well as assembly information.     

Packaging technology for high performance CMOS server FujitsuGS8900

Advanced packaging technologies for CMOS based high performance Fujitsu Global Server GS8900, released in late 1999, are introduced in this paper. Extending a new standard for technological leadership among large-scale enterprise servers, the GS8900 broke the 2000 MIPS barrier in performance for the first time by taking advantages of Fujitsu advanced 0.18 μm copper wiring process and chip/MCM/system packaging capabilities, delivering a doubled performance in comparison to its predecessor. The packaging technologies are uniquely characterized in several aspects. First, the high density stacked via type MCM-D technology features four pairs of CPU tightly coupled multiprocessor and large capacity second caches, the maximum processor terminal count is more than 10,000. The processors are wired onto a multilayer thin film MCM substrate with 153 μm pitch high-density area array lead-free bumps. Secondly, maximum four CPU-MCMs, including 16 CPU processors, and 64 GB main memory modules are mounted on one multilayer system board of high frequency transmission properties. Each MCM is held through a high-density ZIF connector of around 3000 I/Os in a 1.27 mm pitch full matrix, which is assembled on the system board with lead-free solders. Thirdly, advanced cooling technologies are developed for improving the system performance and reliability