Design and analysis of a low-power discrete phase modulator in a 0.13-/spl mu/m logic CMOS process

This letter reports the design and analysis of a low-power discrete constant envelope phase modulator. The modulator discretely changes the phase of a constant envelope carrier according to the input digital data bits. A test chip was fabricated in a 0.13-/spl mu/m logic complementary metal oxide semiconductor process. The modulator consumes 2mA from a 1.2-V supply, has an operating frequency range between 1.5GHz and 3.3GHz, and can support a data rate up to 225Mbps with better than 5.5% error vector magnitude. The modulator can be designed to generate different modulation schemes by digitally controlling the phase and/or amplitude of the carrier, and therefore potentially can be used in software defined radios.     

A Mixed-Loop CMOS Analog GFSK Modulator With Tunable Modulation Index

A new low-power analog Gaussian frequency-shift keying (GFSK) modulator is proposed and implemented in 0.18-CMOS process based on an analog computer implementation of the FM differential equation. The mixed-loop modulation approach is proposed to achieve high data rate and stable carrier frequency. The core of the GFSK modulator is a tunable harmonic oscillator consisting of two G_m-C integrators, whose center frequency can be adjusted by using the on-chip tunable phase-locked-loop (PLL) technique. A simple nonlinear resistor is used to maintain the constant output amplitude. The modulator operates at the center frequency of 2 MHz with the 0.1-0.55 tunable modulation index at 1-Mbps data rate. The modulator draws about 1.8 mA from the 1.8-V power supply and could achieve 2-Mbps data rate with the total harmonic distortion less than 3%.     

A 1.9-GHz-band GaAs direct-quadrature modulator IC with a phaseshifter

A 1.9-GHz-band direct-quadrature modulator IC has been successfully developed for digital portable telephone use. In the 1.9-GHz high-frequency band, both image and carrier rejections as low as -40 dBc have been obtained with a low-power dissipation of 110 mW at a single power supply of 3.1 V, corresponding to a phase error below 1.1. In order to reduce undesired sideband spectral components required for digital modulation, a newly developed circuit configuration that combines a quadrature phase shifter with drivers for amplitude imbalance compensation and makes spectrum efficiency and low-power dissipation possible is used. The modulator IC may be used in enhanced digital mobile radiocommunication systems such as digital portable telephones     

一种应用于无线内窥镜的2.4GHz低功耗ASK发射机

提出了一种应用于无线内窥镜系统的2.4GHz低功耗ASK发射机.为了获得高的数据传输速率,采用了基于混频器的直接上变换发射机结构.为了节省功耗,提出了一种基于电流复用技术的伪差分堆栈结构的A类功放.低功耗发射机由两部分组成:基于恒幅度锁相环(PLL)的20MHz的ASK基带调制器和直接上变换的射频电路.该设计已经采用TSMC 0.25μm CMOS工艺实现并进行了验证.测试结果表明,发射数据速率为1Mbps时,发射机的输出功率为-23.217dBm.采用单2.5V的电源供电下,低功耗发射机消耗的电流约为3.17mA.     

Microwave photonic vector modulator for high-speed wireless digitalcommunications

The authors present the design, realization, and experimental results of a microwave/photonic circuit suitable for high-speed direct digital modulation of microwave signals. The modulator employs a combination of microwave, photonic, and digital techniques to produce a discrete phase and amplitude (i.e., vector) modulated carrier signal. The proof-of-concept demonstration presented in this paper was performed using a carrier frequency of 1 GHz and supports BPSK, QPSK, and 16-QAM. The authors also discuss ways to modify the modulator to simultaneously achieve data rates on the order of several hundreds of Mbs and wideband frequency hopping     

宽带数字调制器设计实现

针对现代数字通信系统中广泛使用的宽带数字调制,分析了其矢量合成原理,并采用统一的FPGA硬件平台、算法软件实现、IF/RF矢量调制器来实现。文中给出了实现电路原理,对实际的幅度与相位不平衡给出补偿解决办法。最后给出了多进制相移键控(MPSK)调制器测试数据,其性能优良,可以满足多频段扩跳频数据传输要求。     

Combined Linear and $Delta$-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters

A combined linear and delta-modulated (DeltaM) switch-mode PA supply modulator for polar transmitters in wireless handsets is designed in a 0.25 mum CMOS process. The modulator employs a DeltaM switch-mode DC-DC buck converter to enhance the efficiency of a linear regulator at backed-off supply voltages and powers. The delta-modulator's noise-shaping characteristic, linear regulator's power supply rejection, digital pre-emphasis of the input envelope, and a closed-loop amplitude path from the PA output are simultaneously used to achieve state-of-the-art modulator performance. The presented supply modulator follows the input signal's envelope with 20 dB output dynamic range, maximum efficiency of 75.5% at an output power of 30.8 dBm, and 75 dB SFDR for envelope signals up to 4 MHz occupied RF bandwidth. For a 1625 kb/s 8 PSK RF input signal at 900 MHz, polar modulation of a commercial low-power GSM-900 PA provides 10 dB ACPR improvement.     

直接正交上变频调制器的镜频抑制与本振泄漏对消技术研究

镜频干扰和本振泄漏是制约直接正交变频技术在无线通信收发信机中应用的主要技术瓶颈之一.通过分析直接正交上变频调制器中引起镜频干扰和本振泄漏的原因,利用逆向校正方法,给出了一种闭环反馈式正交基带信号预失真数字幅相平衡补偿电路,提出了一种通过调节基带信号的直流偏置实现本振泄漏对消的措施,提高了直接正交上变频器的镜频抑制和本振泄漏对消能力,并给出了在小型化CDMA发射机中的应用实例.     

60-GHz Integrated-Circuit High Data Rate Quadriphase Shift Keying Exciter and Modulator (Short Papers)

An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modulator packaged into a small volume of 1.8x2.5X 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.     

Simple oscillators-based readout circuit for low-power biomedical implant system

This paper reports a wireless sensor readout circuit for continuous physiological parameters monitoring including a potentiostat, a data generation unit and a frequency-shift-keying (FSK) modulator unit with the low drop-out (LDO) regulator for biomedical implant system. The potentiostat can generate an output potential of 0.7?V for the data generation unit. The data generation unit is designed based on a relaxation oscillator scheme and can be used to sense a current signal from any amperometric biomedical sensor and convert the signal to a square waveform in which the frequency of the square wave signal is proportional to the sensor current. FSK modulation scheme has been selected for wireless transmission. Designed with a very simple ring oscillator, this modulator integrates the modulation functionality into the oscillator itself by using the data signal to control the oscillation frequency. The prototype circuits have been fabricated in a 0.35???m bulk complementary metal-oxide semiconductor (CMOS) process. Working with a regulated 1.8?V supply, the potentiostat consumes only 2???A of current while the data generation unit can generate around 15.7?kHz output frequency with an input current of 1???A. The FSK modulator consumes a total current of around 19???A for a carrier frequency around 1?MHz. An off-chip demodulator is constructed to demodulate the data signal from the FSK modulator and the demodulated signal has less than 1.6?% variation of frequency.     

用于冷原子干涉仪的声光调制器数字驱动系统

为了满足冷原子干涉实验对激光移频的需求、实现移频速率的精确可控,设计并实现了一个带有操作界面的声光调制器数字驱动与控制系统。该系统由三个部分组成,分别是上位机,微处理器控制芯片,射频信号产生芯片。其中上位机用于收集控制信息;微处理器控制芯片用于根据上位机发送来的控制信息实现对射频信号产生芯片的控制、产生驱动声光调制器晶体的射频信号,从而实现对实验中所需的激光进行移频。该系统可输出频率为0~150 MHz且相位噪声低至-116 dBc/Hz的射频信号,同时可有效控制输出信号的幅度、相位和扫频速率等,该系统提供了满足冷原子干涉实验需求的多种工作模式。     

基于DSP的数字预失真系统设计

为提高无线通信系统的通信质量与效率,提出一种基于DSP自适应数字预失真技术的系统设计。采用TI公司的低功耗、高性能数字信号处理器TMS320VC5502,有效提高了信号处理速度,减少了回路延时。根据信号的幅度,数控衰减器工作在不同的控制模式,以满足不同系统输出功率的要求。结果表明,该系统能有效改善功率放大器的线性度,并将功放的邻道功率比（ACPR）降低了10 dB左右。     

On feasibility of a multiplier-less phase-shifting scheme for digital phase modulation and its VLSI implementation

In this paper, a multiplier-less phase-shifting scheme for digital phase modulation is proposed and its implemantation for very large-scale integration (VLSI) is examined. The abrupt phase shift of carrier waveform, required after each data transition in digital phase-modulation scheme, is realized by incrementing the frequency of a voltage-controlled oscillator (VCO) for a short duration, immediately following the data transition. The momentary increase in VCO frequency is realized by feeding the VCO with narrow control pulses, derived from the baseband data stream using a simple supporting circuit. This work currently deals with the VLSI design for binary phase-shift keying (BPSK). However, the underlying concept is generic and hence capable of implementing other digital phase-modulation schemes, such as, quadrature PSK (QPSK), quadrature amplitude modulation (QAM) etc, with a programmable control circuit for the VCO. Thus, the proposed multiplier-less phase-shifting scheme can find useful application in broadband wireless networks employing adaptive modulation schemes.     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

Gigabit QPSK modulator

We describe a QPSK (quaternary phase shift keyed) modulator operating at gigabit data transmission rates at a carrier frequency of 13 GHz. The modulator circuit can also be operated as a QPSK demodulator. A modulator-de-modulator pair operating in tandem showed clean eye diagrams of the recovered data trains on each port up to l.5 Gbit/s with corresponding error rates of less than 10?11. The circuit can be readily scaled to higher frequencies with a proportional increase in the information rate.     

A digital quadrature modulator with on-chip D/A converter

The first analog IF mixer stage of a transmitter can be replaced with this digital quadrature modulator. The modulator interpolates orthogonal input carriers by 16 and performs digital quadrature modulation at carrier frequencies f/sub s//4, -f/sub s//4,f/sub s//2 (f/sub s/ is the sampling frequency). A 12-b digital-to-analog (D/A) converter is integrated with the digital quadrature modulator. A segmented current source architecture is combined with a proper switching technique to reduce spurious components and to enhance dynamic performance. The digital quadrature modulator is designed to fulfill the spectral, phase, and EVM specifications of GSM, EDGE, and WCDMA base stations. The die area of the chip is 27.09 mm/sup 2/ (0.35-/spl mu/m CMOS technology) and the total power consumption is 1.02 W with 2.8 V at 500-MHz output sampling rate (0.78-W digital modulator, 0.24-W D/A converter).     

A wideband frequency-shift keying wireless link for inductively powered biomedical implants

A high data-rate frequency-shift keying (FSK) modulation protocol, a wideband inductive link, and three demodulator circuits have been developed with a data-rate-to-carrier-frequency ratio of up to 67%. The primary application of this novel FSK modulation/demodulation technique is to send data to inductively powered wireless biomedical implants at data rates in excess of 1 Mbps, using comparable carrier frequencies. This method can also be used in other applications such as radio-frequency identification tags and contactless smartcards by adding a back telemetry link. The inductive link utilizes a series-parallel inductive-capacitance tank combination on the transmitter side to provide more than 5 MHz of bandwidth. The demodulator circuits detect data bits by directly measuring the duration of each received FSK carrier cycle, as well as derive a constant frequency clock, which is used to sample the data bits. One of the demodulator circuits, digital FSK, occupies 0.29 mm/sup 2/ in the AMI 1.5-/spl mu/m, 2M/2P, standard CMOS process, and consumes 0.38 mW at 5 V. This circuit is simulated up to 4 Mbps, and experimentally tested up to 2.5 Mbps with a bit error rate of 10/sup -5/, while receiving a 5/10-MHz FSK carrier signal. It is also used in a wireless implantable neural microstimulation system.     

Design and implementation of current mode circuit for digital modulation

This paper proposes a new current-mode digital modulation circuit. The proposed circuit is MOS only hence, easily integrable. It employs an Extra X Current Conveyor (EX-CCII), two MOS transistors as switches, and a two MOS transistor-based active resistor. The amplitude shift keying/phase shift keying/frequency shift keying (ASK/PSK/FSK) modulator is obtained by proper selection of carriers (I_C1, I_C2). This circuit provides the current output signal at high output impedance, which is favorable for cascading. Also, the circuit is employing only MOS transistors, so it can be monolithically IC implementable. The effects of non-idealities and parasitics of the active element on the circuit performance are also investigated in detail. The functionality of the proposed digital modulator is verified through the Cadence Virtuoso tool using 0.18 μm Generic Process Design Kits parameters with the ±0.9 V supply voltage. The total area of the layout is 968.75 μm². Also, the experimental results are verified by using the IC AD-844 and IC CD4007.     

A compensability RF CMOS mixed-signal interface for implantable system

The implantable microsystem requires the hybrid circuit technology for a brain-machine interface. The paper described a compensability mixed-signal implantable receiver including an analog front-end and a digital processing circuit. The analog circuit consists of mainly an amplifier, an amplitude shift keying (ASK) demodulator, a clock extraction and a power recovery. In this paper, the amplifier and the ASK demodulator are described and provided without the capacitor and the resistor, fully integrated low-power circuit. The processing circuit is designed with the digital technology, so that implementing the correct synchronous signal. The carrier frequency of the circuit is applied in the 10 MHz range; the data rates up to 1 M bit/s are supported, suitable for complex implants such as the brain neural stimulating and so on. The compensability low-power and the high-performance implantable interface using a CMOS technology has been designed, fabricated and verified. All of circuits were implemented in a standard 0.18-μm CMOS process.     

基于直接数字频率合成技术的FM/PM的实现

直接数字频率合成（DDS）是一种可以实现多种调制的新的频率合成技术。调频和调相统称为角度调制。调频是根据调制波的幅度去改变载波的频率;调相是根据调制波的幅度去改变载波的相位。本文在数字电路中实现了模拟调制,大大提高了可移植性和可控性。文章首先介绍了用DDS实现FM、PM调制的基本原理,然后在通用的基带调制硬件平台基础上,给出了一种基于DSP和FPGA实现FM、PM调制的具体方法。最终通过DAC电路,在输出端口得到最终的输出,并且在频谱仪上得到了设定的满足设计要求的所频谱。