不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

不同厚度超薄栅氧化物MOSFET的应力诱导漏电流

研究了不同厚度的超薄栅1.9nm到3.0 nm器件在恒压应力下的栅电流变化.实验结果显示应力诱导漏电流包括两个部分,一部分是由界面陷阱辅助隧穿引起的,另一部分是氧化物陷阱辅助隧穿引起的.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.     

薄膜全耗尽SOIMOSFET单晶体管Latch效应

本文在详细分析各种不同条件下全耗尽ＭＯＳＦＥＴ单晶体管Ｌａｔｃｈ效应测试结果的基础上，较为详细地讨论了单晶体管Ｌａｔｃｈ效应的物理机理，发现单管Ｌａｔｃｈ效应与ＭＯＳＦＥＴ的寄生双极晶体管有着极其密切的关系，最后还给出了相应的改进措施。     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

热载流子诱生MOSFET/SOI界面陷阱的正向栅控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究 .正向栅控二极管技术简单、准确 ,可以直接测得热载流子诱生的平均界面陷阱密度 ,从而表征器件的抗热载流子特性 .实验结果表明 :通过体接触方式测得的MOSFET/SOI栅控二极管R G电流峰可以直接给出诱生的界面陷阱密度 .抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系 ,指数因子约为 0 787     

抗辐射SOI器件栅氧可靠性研究

对抗辐射SOI器件栅氧可靠性进行研究,比较了体硅器件、SOI器件、抗总剂量加固SOI器件的栅氧可靠性,发现SOI材料片的制备与抗总剂量加固过程中的离子注入工艺都会对顶层硅膜造成影响,进而影响栅氧可靠性。最后通过恒压应力法表征栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5 nm栅氧在125℃高温5.5 V工作电压下TDDB寿命达到14.65年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。     

Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.     

SOI抗总剂量辐射加固工艺栅氧可靠性研究

文章对采用了埋层二氧化硅抗总剂量加固工艺技术的SOI器件栅氧可靠性进行研究,比较了干法氧化和湿法氧化工艺的栅氧击穿电荷,干法氧化的栅氧质量劣于湿法氧化。采用更敏感的12.5nm干法氧化栅氧工艺条件,对比采用抗总剂量辐射加固工艺前后的栅氧可靠性。抗总剂量辐射加固工艺降低了栅氧的击穿电压和击穿时间。最后通过恒压法表征加固工艺的栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5nm栅氧在常温5.5V工作电压下TDDB寿命远大于10年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。     

利用MOSFET亚阈I-V特性进行辐射感生界面陷阱的测量

本文利用MOSFET亚阈IV曲线对加固和非加固MOSFET的辐射感生界面陷阱密度进行了测量.分析和讨论了辐射感生的界面陷阱密度依赖于辐射总剂量和辐射剂量率的变化关系     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

SOI／SDB超薄膜全耗尽隐埋n沟MOSFET的解析模型

本文给出了基于SDB材料的无PN结超薄膜全耗尽隐埋n沟型MOSFET的较明确的物理模型,详细分析了它的导电机理,给出了解析表达式.并将本模型的计算结果与实验结果进行了比较,同时进行了一些讨论.     

Effect of floating-body charge on SOI MOSFET design

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage V_T and off-current I_0FF using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in V_T and I_0FF due to hysteretic floating-body charge are quantified for devices in L _eff=0.2- and 0.1-μm design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-μm design space     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

SOIMOSFET二维数值模拟器的设计

介绍了ＳＯＩＭＯＳＦＥＴ 二维数值模拟器的设计过程。耦合和非耦合相结合的迭代方法提高了收敛稳定性和计算效率。考虑了两种载流子的连续性方程及产生复合作用,精度较高。给出了利用该设计方法获得的ＳＯＩＭＯＳＦＥＴ二维体电势分布以及载流子浓度分布的三维输出图形。     

Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces

The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface.     

The effects of high doping on the I-V characteristics of athin-film SOI MOSFET

Modifications of the Ortiz-Conde et al., model which take into account either apparent or physical bandgap narrowing have been presented. The influence of high doping effects is investigated by means of a comparison of the modified models with their original, version for various device parameters. It is shown that the inclusion of bandgap narrowing is essential for accurate simulation of I-V characteristics of a SOI MOSFET in the subthreshold and near-threshold regions. A new analytical model with bandgap narrowing has been derived for the subthreshold region     

超薄SOI应用SALICIDE技术的薄膜厚度优化研究

在ＳＯＩ材料上采用钴自对准硅化物技术，研究了减薄后的ＳＯＩ上钴溅射厚度的优化问题，着重分析了在硅膜厚度一定时钴膜厚度改变、钴膜厚度不变而硅膜厚度变化对硅化物形成后薄层电阻的影响。实验表明，采用Ｔｃｏ：Ｔｓｉ≈１：３．６的近似方法优化钴度膜厚度，会得到薄层电阻最低的硅化接触，改善其接触特性。     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.