X波段砷化镓场效应振荡管

X波段GaAs场效应振荡管是一种专门用于各种微波固体振荡电路的新型器件,尤其对X波段GaAsFET电压控制振荡器(VCO)和介质谐振器振荡器(DRO)更为适合。 本文在对有关资料分析的基础上,提出了设计这一器件的基本原则;概述了器件的基本结构;介绍了器件的参数研究结果和电路应用情况。用该器件制作的X波段FET VCO,得到了800MHz以上的电调范围,在整个电调范围内,输出功率为30～50mW,功率起伏小于1.5dB。     

基于螺旋电感的Wilkinson功分器设计

Wilkinson功分器是一种常用的无源器件,随着通信设备小型化的要求越来越高,无源器件的体积成为其发展瓶颈。为解决这个问题,在分析螺旋电感主要参数及等效电路基础上,提出了一种基于π型等效1/4波长传输线原理,利用集总参数元件组成等效微带线电路的集总参数方法,设计出Si沉底上的螺旋电感和片上电容来实现微波单片集成(MMIC)电路的Wil-kinson功分器。实验表明,同等性能情况下,该方法设计的Wilkinson功分器可以有效减少Wil-kinson功分器的外形尺寸。     

A 4.1 unequal Wilkinson power divider

This letter presents the design and measured performances of a microstrip 4:1 unequal Wilkinson power divider. The divider is designed using the conventional Wilkinson topology with the defected ground structure (DGS). The DGS on the ground plane provides an additional effective inductive component to the microstrip line. This enables the microstrip line to be realized with very high impedance of over 150 Ω. By employing the DGS to the unequal Wilkinson topology, 4:1 power dividing ratio can be obtained easily without any problem in realization, while it has been impractical to fabricate a 4:1 divider using the conventional microstrip line because of very thin conductor width and extremely low aspect ratio (W/H). As an example, a 4:1 divider has been designed and measured at 1.5 GHz in order to show the validity of the proposed DGS and unequal divider. The measured performances of the 4:1 unequal power divider well agree with the exactly same dividing ratio as that expected     

Synthesis of Broad-Band 3-dB Hybrids Based on the 2-Way Power Divider

The synthesis of broad-band 2-way Wilkinson hybrids is well known. The even- and odd-mode analysis results in two equivalent circuits where the synthesis of the odd mode is done by computer optimization. This paper shows an exact synthesis of 2-way Wilkinson power dividers having one isolation resistor, but an arbitrary number of quarter-wave transformers. A large number of circuits have been synthesized with up to 6 quarter-wave transformers. The 2-way Wilkinson hybrid can be extended to a 4-port component. This 4-port component can operate as a 180° or 90° 3-dB hybrid depending on the input port. The hybrid has a high directivity independent of frequency when used as a 180° hybrid. Experimental results are given for a 2-way divider and a 3-dB hybrid built in microstrip with a center frequency of 5 GHz.     

WiIkinson功分器改进和研究

随着通信技术的加速发展,传统的Wilkinson功分器已经无法满足多频及宽带的技术需求。基于ADS仿真设计软件,根据传统的功分器原理和结构,设计了一款谐振频率在900MHz附近的标准Wilkinson功分器。考虑到目前的实际需求,对其结构进行了适当调整和改进,从而仿真设计出了频率在900MHz附近的宽带Wilkinson功分器以及谐振频率为900MHz和2．OGHz的双频Wilkinson功分器,并且对其进行了良率分析,最终的仿真结果实现了预期的传输特性。     

A CMOS frequency synthesizer with an injection-locked frequencydivider for a 5-GHz wireless LAN receiver

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 μm CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc     

A Broadband Quadrature Power Splitter Using Metamaterial Transmission Line

A broadband quadrature power splitter (QPS) is developed using the metamaterial transmission line (MM TL). It consists of a Wilkinson power divider and two phase-adjusting TLs, namely a MM TL and a microstrip (MS). The slope of the phase-response curve of the MM TL is synthesized to be the same as that of the MS along with the 90deg phase increment at two design frequencies. Hence, the broadband quadrature phase difference over the desired frequency range can be obtained. In this letter, the QPS is developed at the center frequency of 2 GHz. Over the frequency range of 1.1-3.5 GHz, an amplitude imbalance of less than 0.9 dB and a phase error of less than plusmn5deg have been experimentally demonstrated.     

Broadband folded Wilkinson power combiner/splitter

A new folded Wilkinson power combiner/splitter has been realized at millimeter-wave frequency with an area that is one half that of the standard two-stage Wilkinson power combiner. The new splitter has an insertion loss of 5dB, an isolation of 15dB and a return loss 15dB from 15 to 45GHz.     

Modified Wilkinson power divider for nth harmonic suppression

This paper presents a structure of the Wilkinson power divider that can suppress the nth harmonic output. The power divider consists of two /spl lambda//4n open stubs, which are located at the center of /spl lambda//4 branches and a parallel connection of a resistor and an inductor, which shunts the output ports. Experimental results show that this power divider suppresses the third harmonic component to less than -40 dB, while maintaining the characteristics of a conventional Wilkinson power divider; featuring an equal power split, a simultaneous impedance matching at all ports and a good isolation between output ports. These results agree quite well with the simulation results.     

一种基于内匹配器件的功率分配器设计

介绍了一种基于内匹配功率管的Wilkinson微带功率分配器设计新思路。传统Wilkinson微带功率分配器在低频段体积大,用于内匹配功率管时很难在规定的尺寸范围内使用,采用高介电常数陶瓷基片辐射损耗大,直流转换效率低。适当引入不连续性,提高端口阻抗值,端口阻抗引入的虚部参与后续匹配网络的新型Wilkinson微带功率分配器,与传统Wilkinson功率分配器相比,体积更小,效率更高,有很好的实用价值。设计的工作频段在5.2～5.8 GHz的Wilkinson微带功率分配器,在整个频带内输出功率大于50 dBm,饱和功率增益高于7 dB,功率附加效率大于30%。     

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

Novel Design Approach for X-Band GaAs Monolithic Analog 1/4 Frequency Divider

A novel analog frequency divider which can generate a 1/4 frequency component is proposed. The frequency divider consists of a dual-gate FET and a two-stage capacitor-resistor coupled amplifier. This circuit configuration also enables achieving a small-size GaAs MMIC analog frequency divider. In this analog frequency divider, the input signal f/sub 0/ is mixed with signal component f/sub 0//x caused by noise or transients in a feedback loop. Then, a (1 -- 1/x)f/sub 0/ IF component is induced and is again mixed with the input signal. This process delivers the f/sub 0//x component regeneratively. Resultant continuous signal components f/sub 0//x and (1-1/x)f/sub 0/ have a harmonic relation when the system reaches a steady state. The f/sub 0//x component can be mainly obtained at an output port of the frequency divider. The operation band was simulated using a SPICE II computer program. The designed bandwidth and conversion gain for the 1/4 frequency divider are 8.5-10.6 GHz and -3 dB, respectively. Based on the simulation, a GaAs monolithic analog 1/4 frequency divider was made and tested. The developed 1/4 frequency divider provides a 8.5-10.2-GHz operation bandwidth and --5+-1-dB conversion gain. The designed and experimental values are in good agreement. The frequency division band can be shifted to higher frequency (10.65-11.2 GHz) by adopting the external matching circuit at the GaAs chip output port. The proposed analog frequency divider circuit can be applied not only for 1/4 frequency division, but also for 1/n frequency division (interger n > 2).     

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-${rm mu}hbox{m}$ CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of $-$ 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm $times$ 0.95 mm.      

一种双带宽UHF主从耦合式LC VCO

为了满足无线通信系统应用需要,设计了一种主从耦合式LC压控振荡器(VCO).基于0.18 μm CMOS标准工艺,由一个5 GHz主VCO和两个起分频作用的从VCO组成,其中主VCO选用PMOS考毕兹差分振荡结构,在两个互补交叉耦合的从VCO的输出端之间设置有注入式NMOS器件以达到分频的目的.仿真及硬件电路实验结果表明,在1.8 V低电源电压下,5 GHz主VCO的调谐范围为4.68～5.76 GHz,2.5 GHz从VCO的调谐范围为2.32～2.84 GHz;在1 MHz的偏频下,5 GHz主VCO的相位噪声为118.2 dBc/Hz,2.5 GHz从VCO的相位噪声为124.4 dBc/Hz.另外,主从VCO的功耗分别为6.8 mW和7.9 mW,因此特别适用于低功耗、超高频短距离无线通信系统中.     

X波段变容管调谐GaAs FET集成VCO的设计

本文介绍了一种宽带FET VCO的S参数设计理论和方法.根据这一理论和方法,用我所的低噪声小功率FET和电调变容管,研制成了X波段变容营调谐的GaAs FBT混合集成VCO.在8GHz频段内,获得500MHz的电调范围,在整个电调范围内,输出功率大于10mW,功率起伏小于0.5dB,直流转换效率大于10%,噪声性能与普通速调管相当,而且体积小,重量轻,成本低.     

A fully integrated CMOS DCS-1800 frequency synthesizer

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

S频段锁相频率合成器的设计

介绍了小数式锁相频率合成器的设计方法及相关理论,分析了影响锁相环相位噪声的主要因素并设计了环路滤波器和Wilkinson功率分配器。由实验结果可知,小数式锁相频率合成器具有很好的相位噪声和较高的频率分辨率。     

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-/spl mu/m SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6/spl plusmn/ 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage.     

A fully integrated V-band PLL MMIC using 0.15-/spl mu/m GaAs pHEMT technology

A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-/spl mu/m GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35/spl times/1.80 mm/sup 2/. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip.