A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved     

On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM

On-chip test circuitry that provides 8-b-deep emitter-coupled logic (ECL) level patterns to 12 input pads of a 512-kb CMOS ECL static RAM (SRAM) at cycle times as fast as 1.4 ns has been built in a 0.8- mu m CMOS technology with L/sub eff/=0.5 mu m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide an optimum setup time and data-valid windows as the operating frequency changes is described. Measured results and extensive simulation demonstrate the stability of the on-chip test circuitry for cycle times of 1.4-50 ns. The on-chip test circuitry makes it possible to test the SRAM chip at its pipelined cycle time. In addition, the speed of the on-chip test circuitry will track future technology improvements, making it possible to generate test patterns as SRAM performance continues to improve.<>     

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 klogic gates and on-chip test circuitry

A soft-error-immune, 0.9-ns address access time, 2.0-ns read/write cycle time, 1.15-Mb emitter coupled logic (ECL)-CMOS SRAM with 30-ps 120 k ECL and CMOS logic gates has been developed using 0.3-μm BiCMOS technology. Four key developments ensuring good testability, reliability, and stability are on-chip test circuitry for precise measurement of access time and for multibit parallel testing, a memory-cell test technique for an ECL-CMOS SRAM, a highly stable current source with a simple design using a current mirror, and a soft-error-immune memory cell using a silicon-on-insulator (SOI) wafer. These techniques will be especially useful for making the ultrahigh-speed, high-density SRAM's used as cache and control storages in mainframe computers     

A 9-ns 1-Mbit CMOS SRAM

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.<>     

Dynamic Power Supply Current Testing for Open Defects in CMOS SRAMs

The detection of open defects in CMOS SRAM has been a time consuming process. This paper proposes a new dynamic power supply current testing method to detect open defects in CMOS SRAM cells. By monitoring a dynamic current pulse during a transition write operation or a read operation, open defects can be detected. In order to measure the dynamic power supply current pulse, a current monitoring circuit with low hardware overhead is developed. Using the sensor, the new testing method does not require any additional test sequence. The results show that the new test method is very efficient compared with other testing methods. Therefore, the new testing method is very attractive.     

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kbECL-CMOS SRAM

A 1.5-ns access time, 78-μm² memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers     

一款异步256kB SRAM的设计

在集成电路设计制造水平不断提高的今天,SRAM存储器不断朝着大容量、高速度、低功耗的方向发展。文章提出了一款异步256kB(256k×1)SRAM的设计,该存储器采用了六管CMOS存储单元、锁存器型灵敏放大器、ATD电路,采用0.5μm体硅CMOS工艺,数据存取时间为12ns。     

A 3.3-V 12-ns 16-Mb CMOS SRAM

A 16-Mb CMOS SRAM having an access time of 12 ns under a 3.3-V supply has been developed with a 0.4-μm process technology. An address access time of 12 ns has been achieved by an optimized architecture, the use of an automated transistor size optimizer, and a read-bus midlevel preset scheme (RBMIPS). For better yield and efficient testing, an on-chip test circuit with three test modes has been implemented     

65nm SRAM传统静态指标的测试方案及研究

65 nm及其以下工艺,工艺波动对SRAM性能影响越来越大.SRAM读写噪声容限能够反映SRAM性能的好坏,对于预测SRAM良率有着重要的作用.采用一种新型测试结构测量SRAM读写噪声容限(即SRAM传统静态指标),该测试结构能够测量65 nm SRAM在保持、读、写三种操作下的指标:Hold SNM,RSNM,N-c...     

Soft-defect detection (SDD) technique for a high-reliability CMOSSRAM

A complete data retention test of a CMOS SRAM array accomplished at room temperature using the soft-defect detection (SDD) technique is reported. The SDD technique uses a connectivity analysis and cell-array current test to detect physical open faults that can cause data retention failures. An extensive circuit analysis was made to establish the operation theory and special circuit design features required for SDD. Complete SDD circuits have been developed and implemented into a 16 K CMOS SRAM module for a 32-b microcontroller. Full operation and effectiveness of the SDD technique were verified from a special experimental 16 K CMOS RAM module with built-in defective cells. the SDD technique can accomplish not only the retention test at room temperature, but also the detection of other defects that were heretofore impractical to detect using the conventional retention test technique of high-temperature bakes and functional tests     

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an accesstime of 550 ps and an operating frequency of 900 MHz

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-μm MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A 1-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-μm BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high operating frequency of 900 MHz with a power dissipation of 43 W     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

Single-ended SRAM with high test coverage and short test time

The advantages of low power dissipation and smaller chip area for single-ended SRAMs are well known. In this paper, we present the configuration and test strategy of a single-ended, six-transistor SRAM. The benefits of short test time, no retention test, and high test coverage are verified. The goals of low power, high quality control, and short test time of the full CMOS SRAM can be achieved     

一种512 Kbit同步高速SRAM的设计

设计了一种深亚微米 ,单片集成的 5 1 2 K( 1 6K× 32位 )高速静态存储器 ( SRAM)。该存储器可以作为IP核集成在片上系统中。存储器采用六管 CMOS存储单元、锁存器型敏感放大器和高速译码电路 ,以期达到最快的存取时间。该存储器用 0 .2 5μm五层金属单层多晶 N阱 CMOS工艺实现 ,芯片大小为 4.8mm× 3.8mm。测试结果表明 ,在 1 0 MHz的工作频率下 ,存储器的存取时间为 8ns,工作电流 7m A。     

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns     

Analysing NBTI Impact on SRAMs with Resistive Defects

Density’s increase in Static Random Access Memory (SRAM) has become an important concern for testing, since new types of defects, that may occur during the manufacturing process, are introduced. On the one hand, new manufacturing defects may lead to dynamic faults, which are considered one of the most important causes of test escape in deep-submicron technologies. On the other hand, the SRAM’s robustness is considered crucial, since it may affect the entire SoC. One of the most important phenomena to degrade SRAM reliability is Negative-Bias Temperature Instability (NBTI) causing the memory cells’ aging. In this context, the paper proposes to analyse the impact of NBTI on SRAM cells with resistive defects that eventually escape manufacturing test and, with aging, may generate faults over time. Finally, SPICE simulations adopting a commercial 65 nm CMOS technology library have been performed in order to estimate NBTI’s precise impact over time.     

An effective BIST scheme for SRAM full speed test

This article presents a novel built-in self-test (BIST) scheme at full speed test where access time test is performed. Based on normal BIST circuits, we harness an all digital phase locked loop to generate a high-frequency clock for static random access memory (SRAM) performance test at full speed. A delay chain is incorporated to achieve the four-phase clock. As inputs to SRAM, clock, address, data are generated in terms of the four-phase clock. Key performance parameters, such as access time, address setup and hold times, are measured. The test chip has been fabricated by United Microelectronics Corporation 55?nm CMOS logic standard process. According to test results, the maximum test frequency is about 1.3?GHz, and the test precision is about 35?ps at the typical process corner with supply voltage 1.0?V and temperature 25°C.     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

Stacked CMOS SRAM cell

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.