Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

A new technique to extract oxide trap time constants in MOSFET's

A new technique to determine oxide trap time constants in a 0.6 μm n-MOSFET subject to hot electron stress has been proposed. In this method, we used GIDL current as a direct monitor of the oxide charge detrapping-induced transient characteristics. An analytical model relating the GIDL current evolution to oxide trap time constants was derived. Our result shows that under a field-emission dominant oxide charge detrapping condition, Vgs=-4 V and Vds=3 V, the hot electron stress generated oxide traps exhibit two distinct time constants from seconds to several tens of seconds     

Separation of interface and nonuniform oxide traps by the DCcurrent-voltage method

Areally nonuniform distribution of oxide charge gives a significant distortion in the gate capacitance and subthreshold DC drain current versus DC gate voltage characteristics. This distortion prevents a reliable determination of the spatial profile of interface and oxide traps generated when a MOS transistor is subjected to channel hot carrier stress. A new procedure is demonstrated which separates the nonuniform oxide charge distribution from interface traps by combining the analysis of two experimental DC characteristics: the subthreshold drain-current and the DC base recombination current versus the gate voltage     

Hot hole stress induced leakage current (SILC) transient in tunneloxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f^-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed     

Analysis of the DCIV peaks in electrically stressed pMOSFETs

This paper presents the effects of Fowler-Nordheim (FN) and hot-carrier (HC) stress in the direct-current current voltage (DCIV) measurements. The effect of interface trapped charge on DCIV curves is reported. Stress-induced oxide charge shifts the DCIV peaks, while stress-induced interface trapped charge causes a spread in the DCIV peaks. It is found that under HC stress, when the absolute value of stress gate voltage changes from low to high, the interface trap spatial location moves from the drain region to the channel region. It is inferred that the generation of oxide charge in the drain region is a two-step process. For short stress times, electrons mainly fill the process-induced neutral oxide traps, while for long stress times, electrons fill the stress created electron traps     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Base current relaxation transient in reverse emitter-base biasstressed silicon bipolar junction transistors

The base current relaxation transient following reverse emitter-base (EB) bias stress and its effect on time-to-failure (TTF) determination are examined in self-aligned and nonself-aligned silicon bipolar junction transistors (BJTs) with thermal and deposited base oxide. A quantitative model indicates that the transient is due to a reduction of the stress-generated positive charge trapped in the oxide layer near the emitter-base junction due to holes tunneling from oxide hole traps to silicon band states or SiO₂/Si interface traps. The neutral oxide hole traps may be quickly recharged through hole tunneling or hole injection into the oxide during further reverse-bias stress. A delay time of ~10^-3 s was observed after the termination of stress before base current relaxation begins, which affects the extraction of the ac operation TTF from dc stress measurements     

Dynamic oxide voltage relaxation spectroscopy

A new method for trap characterization of oxidized silicon is described. The Dynamic Oxide Voltage Relaxation Spectroscopy (DOVRS) is an improved version of the formerly proposed Oxide Voltage Relaxation Spectroscopy (OVRS) technique which applies a periodic long duration constant current for tunneling injection. It has been demonstrated that the new technique can be used not only to separate and identify the oxide trap from interface trap, but also to separate and determine the centroid from the oxide trap density generated in the MOS system by the tunneling current stress. In the pulse constant current mode, the OVRS measurement can be completed instead of using the double current-voltage technique. Thus the new method results in more accurate and quicker measurements of the oxide trap centroid. Analytical expressions for computing the paramaters of the interface and oxide traps are derived. The effect of the channel carrier mobility on the spectroscopy is also considered. Two types of oxide and two types of interface traps were observed at a pulse constant Fowler-Nordheim current stress by the new method of DOVRS     

Donor-like interface trap generation in pMOSFET's at roomtemperature

The generation of donor-like interface traps under room temperature bias stress is observed. This generation process is insensitive to the gate polarity, hot carrier stress, and positive charge formation in the gate oxide. It requires the simultaneous presence of boron- and water-related species. The generated interface traps are nonuniformly distributed along the channel     

Two types of neutral electron traps generated in the gate silicon dioxide

Electron trap generation in the gate oxide is a severe problem for the reliability of MOS devices, since it can cause stress-induced leakage current (SILC) and eventually lead to oxide breakdown. Although much effort has recently been made to understand the mechanism for the trap generation, the properties of the generated traps have received relatively less attention. The objective of this paper is to present unambiguous results, showing that two different types of neutral electron traps can be created by the same stress and to compare the properties of these two types of traps. Differences have been found in terms of their generation kinetics, trap filling, detrapping, and refilling after detrapping. The results also indicate that the energy levels of these two types of traps are different.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Hot-hole-induced negative oxide charges in n-MOSFETs

We investigate the generation of electron traps by hole injection during hot-carrier stressing of n-MOSFETs. These generated electron traps are filled by an electron injection following the primary hole stress. The effect is proven and quantified by monitoring the detrapping kinetics in the multiplication factor and the charge pumping current. The traps are located in the oxide within the first few nanometers to the interface. An interaction of those traps with interface states is found in that charged electron traps inhibit charging or uncharging of interface states. The kinetics of hot-carrier-induced fixed negative charges in n- and p-channel MOSFET's are compared showing significant differences in the properties of the two species of traps. Hole-induced electron traps are located much closer to the interface and their energetic level is deeper. Finally, a method is presented that allows the quantification of the effect for reliability purposes. We conclude that under digital and analog operation conditions in which hole effects cannot completely be ruled out, this effect has to be considered.<>     

Low-frequency noise spectroscopy of polycrystalline siliconthin-film transistors

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

Spatial distribution of interface traps in DeMOS transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.     

Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

New findings of interface trap passivation effect in negative bias temperature instability (NBTI) measurement for p-MOSFETs with SiON gate dielectric are reported. We show evidence to clarify the recent debate: the recovery of V/sub th/ shift in the passivation phase of the dynamic NBTI is mainly due to passivation of interface traps (N/sub it/), not due to hole de-trapping in dielectric hole traps (N/sub ot/). The conventional interface trap measurement methods, dc capacitance-voltage and charge pumping, seriously underestimate the trap density N/sub it/. This underestimation is gate bias dependent during measurement, because of the accelerated interface trap passivation under positive gate bias. Due to this new finding, many of previous reliability studies of p-MOSFETs should be re-investigated.