Optimum selection of capacitive array for multibit Sigma-Delta modulators without DEM

A method for a smart selection and sequencing of unity capacitors in a multibit digital-to-analog converter (DAC) that improves the linearity is proposed. The approach, suitable for the DAC nonlinearity correction in Sigma-Delta modulators, obtains better results than dynamic element matching. The key of the proposed technique is an off-line self-measurement of mismatches with the available hardware. The results significantly improve when redundant DAC capacitors are introduced. Hence, the capacitors are selected from a set that is larger than required. An affordable silicon area overhead introduced by the redundant capacitors avoids extra power consumption, that is unavoidable in other methods during the normal operation of the converter.     

DISCO: a graphical methodology for the design of Sigma-Delta modulators

A MATLAB^TM toolbox for the design and simulation of continuous time (CT) and discrete time Sigma-Delta modulators is presented. The design of Sigma-Delta modulators is performed by placing the poles and zeros of the loop filter and estimating the resulting noise transfer function and signal transfer function. For this, the toolbox offers a graphical user interface for direct user interaction. Several additional functions, e.g. excess loop delay compensation, are made available to the designer. Further, the designed loop filter can be synthesized in CIFF and CIFB topology or CRFF and CRFB in the case of a bandpass modulator. Additionally, the toolbox offers the design of a closed loop Sigma-Delta sensor readout having the sensor as part of the loop filter. Furthermore, several typical non-idealities of CT Sigma-Delta modulators such as real opamp behavior, excess loop delay, and jitter, are simulated with a tremendously speed up via the application of the lifting approach.     

Switched capacitor analog modulo integrator for application in open loop Sigma-Delta modulators

We introduce the switched capacitor analog modulo integrator, which to our knowledge is a new circuit. We introduce the amplitude modulated open loop ΣΔ modulator (OLSDM), which is an analog modulo integrator followed by a quantizer and a modulo differentiator. The mathematical equivalence between low pass ΣΔ modulators and OLSDM is explained. Behavioral simulations confirm the equivalence. The necessary circuit, a switched capacitor analog modulo integrator, is explained in detail. Behavioral level simulations in SPICE of the analog modulo integrator verify the function, and prove the concept of amplitude modulated OLSDM.     

The design of high-order bandpass sigma-delta modulators using low-spread single-stage structure

A structure for single-stage high-order bandpass sigma-delta modulators (BPSDMs) is presented. The proposed structure introduces an additional internal path in each resonator, thus, adding one degree of freedom in coefficient determination. Coefficient spread can therefore be reduced, resulting in significantly reduced capacitance area in switched-capacitor BPSDM circuits. High-order BPSDMs with different quality factors (Q) are demonstrated. It shows that coefficient spread is significantly reduced, especially for high-Q applications. For comparable eighth-order 3-bit BPSDMs, the maximum coefficient spread are respectively 15369 and 7693 for conventional cascade-of-resonator-with-feedback (CRFB) and cascade-of-resonator-with-feedforward (CRFF) designs, and 114 for the proposed structure. For an eighth-order 1-bit example, these respective values are 8994, 2638, and 74. With coefficient mismatch, peak signal-to-noise ratio (PSNR) degradation of the proposed structure is less than those of the CRFB and CRFF structures, demonstrating reduced sensitivity to component mismatch. Hence, the proposed structure can reduce chip area and ease circuit implementation of BPSDMs.     

小面积、微功耗增量型Sigma-Delta ADC设计

模拟数字转换器（ADC）是智能化传感器的一个重要组成部分。阵列型传感器应用对ADC的功耗及芯片面积都具有较高的要求,同时传感器本身特性要求ADC具有较高的精度,对阵列型传感器用 ADC 的设计提出了挑战。在分析各类型 ADC 的性能优劣势的基础上,提出了应用增量型Sigma-Delta ADC来设计阵列型传感器应用。介绍了增量型Sigma-Delta ADC的架构设计以及电路设计,并在0.18mm CMOS工艺下流片。在40kS/s的转换速度下,所设计的ADC达到了15bit的精度,功耗为58mW,单个ADC的芯片面积为10mm×530mm。测试结果表明增量型Sigma-Delta ADC非常适合于阵列型传感器应用。     

异步Sigma-Delta调制的系统级设计

异步sigma-delta调制(asynchronous sigma-delta modulator,ASDM)在30-MHz带宽VDSL线路驱动器应用中,输出缓冲器的传输延时限制了系统的性能。本文采用时域分析的方法,得到了1阶、2阶ASDM系统的振荡频率与输入信号之间的关系,并给出了系统增益的表达式和3次谐波计算的经验公式,经Matlab仿真验证,具有较高的精度。本文的工作对ASDM的其他应用也具有较好的指导作用。     

Σ-Δ模拟/数字转换器综述

Σ-ΔA/D转换器是利用速度换取精度的高精度模拟/数字转换器。文章分析了Σ-ΔA/D转换器的产生、组成和优势,重点介绍了Σ-Δ调制器结构及其性能指标,简要介绍了数字抽取滤波器。对Σ-ΔA/D转换器国内外发展状况进行了全面的分析。在此基础上,论述了Σ-ΔA/D转换器未来的发展趋势。     

三阶级联Sigma-Delta调制器设计

介绍2-1级联的三阶调制器设计结构，讨论信号比例系数、积分增益系数和电路非理想特性对调制器系统的性能影响：运用SIMULINK对调制器建模并仿真，模型中考虑．开关电容积分器的非理想因素对整个调制器的影响．并通过调整信号比例和积分增益系数来确定调制器性能和电路要求。当采样率为125和时钟频率2．50MHz时．该模型结构得到93dB的信噪失真比，可应用于实际的电路系统。     

∑△调制器输出码流FFT谱分析的探讨

∑△调制器输出码流的频谱中含有大量高频噪声，在对其进行FFT谱分析时，需要加窗函数抑制这些高频噪声对基带噪底的泄漏。由于∑△调制器输出码流的噪声主要是高频噪声，因此需要滚降衰减较大的窗函数，窗函数选择不当会使其有效位数有2-6位的下降。实例表明，对于超过20bit精度的∑△调制器，选用Balckmanharris窗比Harming窗更合适。     

Σ-Δ型A/D转换器基本原理解析

Σ-Δ型A/D转换器以其独特的优势,广泛应用于转换速率在每秒百千次以下的场景中。其核心Σ-Δ调制器虽然结构简单,但工作原理理解却不易,我们独辟蹊径,从初学者易于理解的角度切入,进行原理阐述,然后回归到实际的结构图,最后给出了Σ-Δ调制器的PSpice仿真验证,解决了初学者理解Σ-Δ型A/D转换器工作原理的难题。     

用于Sigma-Delta调制器的低电压跨导运算放大器

跨导运算放大器是模拟电路中的重要模块,其性能往往会决定整个系统的效果.这里设计了一种适用于高阶单环Sigma-Delta调制器的全差分折叠式共源共栅跨导运算放大器.该跨导运算放大器采用经典的折叠式共源共栅结构,带有一个开关电容共模反馈电路.运算放大器使用SIMC 0.18 μm CMOS混合信号工艺设计,使用Spectre对电路进行整体仿真,仿真结果表明,负载电容为5 pF时,该电路直流增益可达72 dB、单位增益带宽91.25 MHz、相位裕度83.35°、压摆率35.1 V/μs、功耗仅为1.41 mW.本设计采用1.8 V低电源电压供电,通过对电路参数的优化设计,使得电路在低电压条件下仍取得良好的性能,能满足Sigma Delta调制器高精度的要求.     

POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters

While one-bit ΣΔ modulators are widely used in Analog to Digital conversion stages due to their inherent linearity and precision, it is less common for the entire digital processing path to operate in single bit mode at the oversampled rate of the conversion system. The conventional approach has been to decimate the signal bit stream after conversion and for the remaining processing to be performed in standard multi-bit binary at the Nyquist rate and with a resolution mandated by the dynamic range and noise. Using a Finite Impulse Response filter design as an example, we compare the area and performance of this conventional approach with the alternative single bit approach that operates directly on the ΣΔ data stream using ternary coefficients {?1, 0, +1} derived from the ΣΔ modulation of the target impulse response. Filters exhibiting approximately equivalent spectral performance in the two alternative approaches were developed using VHDL and simulated using some commercial FPGA types. In these experiments, the single-bit filters using ternary coefficients were found to dissipate less power compared to the conventional approach despite their need to operate at much higher clock rates. They also exhibit up to 40% higher performance and offer useful area savings at lower filter orders. At higher orders, the ΣΔ approach retains its power and performance advantages but exhibits slightly higher chip area. The simplicity and low power of the ΣΔ approach makes it applicable to mobile communication processing using low cost FPGA technology.     

Generalized topologies of single-stage input-current-shapingcircuits

In this paper, two generalized topologies of single-stage input-current-shaping (S²ICS) circuits are derived: S² ICS circuits with two-terminal ICS cells and S²ICS circuits with three-terminal ICS cells. It is shown that most of the recently published S²ICS circuits belong to either of the two generalized topologies. It is also shown that the two generalized S²ICS topologies are functionally equivalent. Based on the generalized approach, a few new S²ICS circuits are developed. Experimental results obtained on a selected pair of S²ICS circuits with two-terminal and three-terminal ICS cells are also provided     

Ultrafast, multi-THz-detuning, third-order frequency conversion insemiconductor quantum-well waveguides

The near-band-edge resonance nonlinearity of semiconductor quantum wells has been used to obtain nondegenerate four-wave mixing over a multi-THz frequency detuning range, with large conversion efficiencies. In 1-mm-long, passive AlGaAs/GaAs single-quantum-well waveguides, conversion efficiencies up to -8.5 dB with relatively flat response have been observed over a 7.5-THz range (2.2% of the band gap). The nonlinearity is ultrafast and primarily reactive. The potential application of this technique to wavelength shifting devices is discussed     

A 3.3 V, 10 Bits, Clock-Feedthrough Compensated Switched-Current Second Order Sigma-Delta Modulator

This article presents a low-pass sigma-delta modulator for Analogue-to-Digital conversion. The circuit uses a switched-current technique which presents a well known drawback called clock feedthrough. This phenomenon induces an error on the output signal value. In order to cancel the clock feedthrough effect, we use a new method based on a current feedback loop. The circuit is designed in 0.8 μm AMS “Austria Mikro Systems” single poly CMOS process. Measurements of the modulator are performed under A/D converters characterisation system, and show 55 dB dynamic range at 2.048 MHz sampling rate with 8 kHz input frequency bandwidth. These characteristics are suitable for audio applications.     

The Structure of Quantization Noise from Sigma-Delta Modulation

When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.     

一种新型的级联并行过采样∑Δ调制器结构

本文提出了一种基于时域交织技术的级联∑Δ调制器新结构,保留了原有时域交织结构的速度优势,克服了它的缺点,且电路简单,具有实用价值.对1-1级联、4路并行的情况进行模拟的结果表明:新结构比普通2阶∑Δ调制器,相同时钟速率下转换精度提高3bit,同样精度要求下转换带宽扩大一倍,对各路增益失配等电路非理想因素不敏感.     

应用于数字音频的二阶Sigma-Delta调制器设计

设计了一个应用于数字音频处理芯片的Sigma-Delta调制器,为了提高模数转换器的解析度,采用稳定的二阶结构,通过提高过采样率来实现.采用HJTC0.18μmCMOS工艺,在1.8V电压下设计过采样率为256的二阶开关电容调制器,使用Hspice和MATLAB对电路进行了仿真分析,结果表明可以达到92.5dB的信噪比,有效位数约16位.     

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise modeling of the memory cell is derived. Based on this modeling, the analysis is extended to other circuits of higher level in the modulator hierarchy such as integrators and resonators. After that, the study is extended to the modulator level, considering two fundamental architectures: a 2nd-order LowPass ΣΔM (2nd-LPΣΔM) and a 4th-order BandPass ΣΔM (4th-BPΣΔM). The noise shaping degradation caused by the linear part of SI errors is studied in the first part of the paper. This study classifies SI non-idealities in different categories depending on how they modify the zeroes of the quantization noise transfer function. As a result, closed-form expressions are found for the degradation of the signal-to-noise ratio and for the change of the notchfrequency position in the case of 4th-BPΣΔMs. The analysis is treated considering both the isolated and the cumulative effect of errors. In the second part of the paper the impact of non-linear errors on the modulator performance is investigated. Closed-form expressions are derived for the third-order harmonic distortion and the third-order intermodulation distortion at the output of the modulator as a function of the different error mechanisms. In addition to the mentioned effects, thermal noise is also considered. The most significant noise sources of SI ΣΔMs are identified and their contributions to the input equivalent noise are calculated. All these analyses have been validated by SPICE electrical simulations at the memory cell level and by time-domain behavioural simulations at the modulator level. As an experimental illustration, measurements taken from a 0.8 μm CMOS SI 4th-BPΣΔM silicon prototype validate our approach.     

用于MEMS传感器的三阶∑-△调制器设计

提出一种基于CIFB结构的新型三阶2-1级联∑-△调制器,设计了各级参数和数字校正电路,分析了积分器运算放大器的压摆率对信号带宽的影响;利用Matlab Simulink,对该调制器进行行为级仿真.在过采样率为128、输入信号带宽为50 kHz时,可达到93.8 dB的信噪比和15.30住的精度.该结构具有输入信号低失真的优点,可用于MEMS传感器的数据处理电路.