Semiconductor device simulation

The most effective way to design VLSI device structures is to use sophisticated, complex two-dimensional (2D) and three-dimensional (3D) models. This paper and its companion [1] discusses the numerical simulation of such device models. Here we describe the basic semiconductor equations including several choices of variables. Our examples illustrate results obtained from finite-difference and finite-element implementations. We stress the necessary 3D calculations for small-size MOSFET's. Numerical results on inter-electrode capacitive coupling are included.     

Logic and memory with nanocell circuits

Molecular electronics is an emerging field that seeks to build faster, cheaper, denser computers from nanoscale devices. The nanocell is a molecular electronics design wherein a random, self-assembled array of molecules and metallic nanoparticles is addressed by a relatively small number of input/output pins. The challenge then is to program the nanocell post-fabrication. We have previously demonstrated the ability to program individual simulated nanocells as logic gates. In this paper, we further explore the problem of programming nanocells and consider connecting nanocells into circuits using bistable latches at the interconnects. These latches are critical because they permit signal restoration. Simulated nanocell circuits for logic and memory are presented here.     

Semiconductor memory trends

In retrospect, over the past decade and a half, semiconductor memories have been in the stage of youthful growth. A thousand times increase in density and a ten times increase in speed have been recorded. Semiconductor memories have thus been a key element in the revolutionary development of digital electronics. Today, they are undoubtedly entering their age of maturity. Their density limit will be on the order of 100 Mbits per chip, roughly a hundred times the state of the art, and additional speed increase will be less than ten times. Nonetheless, the challenge is still there. Efforts to search for new technology which will actually bring out, in a cost-effective manner, the remaining density and speed potential of semiconductor memories are essential. A thorough investigation is needed to clarify and overcome mechanisms of phenomena which dominate device reliability and degradation. Integrating various data processing, as well as data storing, functions on a chip is the key to adding values to semiconductor memories.     

MOSFET memory circuits

Metal-oxide-semiconductor first effect transistors (MOSFETs) are currently being used in a variety of memory applications. The requirements of memory usage and the characteristics of MOSFET devices and technology have led to a number of unique circuits for these applications. Organization and design considerations of memory systems using MOSFET devices are reviewed, and examples of specific circuits are presented and analyzed. These include random access cells, shift registers, read only storage, and on-chip support circuits; both complementary and noncomplementary circuits are discussed.     

Semiconductor device simulation at NTT

The current status of semiconductor device simulation at NTT is described. Device simulators at NTT are classified into two categories. One is the conventional macroscopic approach and the other is microscopic particle analysis using a Monte Carlo method. In this paper, these simulators are introduced together with the more interesting results. Through these examples, it is demonstrated that the device simulation takes an important role for accurate modeling of semiconductor devices.This report also concludes that the choosing the best simulation program for a given problem is the key to obtain effectively an accurate solution.     

Built-in redundancy analysis for memory yield improvement

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.     

半导体器件工艺中热电偶可靠性测温

本文介绍了半导体器件工艺中利用热电偶测温的原理、性能以及如何对热电偶误差进行修正补偿。     

Semiconductor device reliability vs process quality

This paper describes a method for defining a quantitative model relating “quality” expressed in terms of parameter distributions and “reliability” expressed in terms of failure rates. This model makes it possible to generate a more realistic failure rate estimate for semiconductor devices. With this model, failure rate predictions based on conventional life test data and on process parameter distributions, can be defined.     

Protective device for MOS integrated circuits

Two protective devices for MOS integrated circuits have been extensively tested and proved feasible. They also perform more reliably than conventional Zener diodes. One of them has been used in the fabrication of a dual 25-bit MOS and MNOS integrated shift register and performed reliably.     

Switched-current memory circuits for high-precision applications

We discuss circuit parameters that limit the precision of basic dynamic current-memory cells. In addition to analyzing current-copying errors caused by the finite output conductances of the current sources and by the clock-feedthrough (CFT) of the feedback switches, we analyze the noise performance of the basic memory cell. To reduce CFT and noise, we propose a novel circuit based on Miller capacitance-enhancement. Measurement results of memory cells integrated in a 1-μm CMOS process confirm the theoretical findings; with our CFT and noise reduction technique based on Miller enhanced capacitance and dummy switches, we achieve a dynamic range of 11 b at clock frequencies greater than 100 kHz     

Magnetic bubble memory linear interface circuits

Two bipolar integrated circuits are described which provide the write and sense functions required by magnetic bubble memory systems, both organized in four-channel format to minimize board area occupied. The write driver circuit has a 300 mA drive capability and includes on-chip circuitry which prevents fusing of the delicate bubble `hairpin' structure under fault conditions. The sense amplifier has programmable sensitivity in the range of 1 mV to 10 mV and allows the bubble device to be directly coupled to the differential input while tolerating DC offsets of up to /spl plusmn/150 mV without significantly modifying sensitivity.