RF noise in 0.18-/spl mu/m and 0.13-/spl mu/m MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF/sub min/) in deep submicrometer MOSFETs. A lowest NF/sub min/ of 0.93 dB is measured in 0.18-/spl mu/m MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 /spl mu/m shows larger NFmin than the 0.18-/spl mu/m case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-/spl mu/m MOSFET gives higher NF/sub min/ due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF/sub min/ for further scaling down of the MOSFET.     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

Optimized retrograde N-well for 1-/spl mu/m CMOS technology

Using experiment and simulation, transistors in a high-energy implanted N-well are designed for optimum device performance suitable for 1-/spl mu/m CMOS technology. The effect of process parameters on device performance is obtained. Superior body effect, junction capacitance, punchthrough voltage, and subthreshold slope are achieved for 1-/spl mu/m n- and p-channel transistors. With shallow P/P+ epitaxial material, this retrograde N-well approach also provides latch-up immunity for high-density CMOS.     

Monolithically integrated boost Converter Based on 0.5-/spl mu/m CMOS Process

Today and in the future, a huge market arises for mobile power . Efficient performance, functionality, small profile and low cost are the most desired features for mobile power management integrated circuits. Compared with the discrete-switching dc-dc converter, monolithic integration offers many benefits and new design challenges. In this paper, a monolithically integrated high-efficiency boost dc-dc converter for nickel metal hydride or alkaline battery-powered applications is designed based on the low-voltage CMOS process. Several novel concepts are proposed for compensator design, low-voltage startup, light-load efficiency and power device optimization.     

High-performance 1-Gb-NAND flash memory with 0.12-/spl mu/m technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

1.31-1.55-/spl mu/m phased-array demultiplexer on InP

The first demultiplexers on InP at 1.31-1.55 /spl mu/m based on low-order waveguide arrays have been fabricated and characterized. We show the calculated and measured spectral responses of two devices with 6 and 10 waveguides in the grating. The on-chip loss of the devices is 4.5 dB and the crosstalks are down to -25 dB. Thanks to their large bandwidth, the devices are polarization insensitive and no strong influence of the temperature is seen.     

1.5-/spl mu/m InGaAsP-InP slab-coupled optical waveguide lasers

We report the demonstration of high-power semiconductor slab-coupled optical waveguide lasers (SCOWLs) operating at a wavelength of 1.5 /spl mu/m. The lasers operate with large (4/spl times/8 /spl mu/m diameter) fundamental mode and produce output power in excess of 800 mW. These structures have very low loss (/spl sim/0.5 cm/sup -1/) enabling centimeter-long devices for efficient heat removal. The large fundamental mode allows 55% butt-coupling efficiency to standard optical fiber (SMF-28). Comparisons are made between SCOWL structures having nominal 4- and 5-/spl mu/m-thick waveguides.     

1.58-/spl mu/m broad-band erbium-doped tellurite fiber amplifier

This paper describes the development of a 1.58-/spl mu/m broad-band and gain-flattened erbium-doped tellurite fiber amplifier (EDTFA). First, we compare the spectroscopic properties of various glasses including the stimulated emission cross sections of the Er/sup 3+4/ I/sub 13/2/ /sup 4/I/sub 15/2/ transition and the signal excited-state absorption (ESA) cross sections of the Er/sup 3+4/ I/sub 13/2/ - /sup 4/I/sub 9/2/ transition. We detail the amplification characteristics of a 1.58-/spl mu/m-band EDTFA designed for wavelength-division-multiplexing applications by comparing it with a 1.58-/spl mu/m-band erbium-doped silica fiber amplifier. Furthermore, we describe the 1.58-/spl mu/m-band gain-flattened EDTFA we developed using a fiber-Bragg-grating-type gain equalizer. We achieved a gain of 25.3 dB and a noise figure of less than 6 dB with a slight gain excursion of 0.6 dB over a wide wavelength range of 1561-1611 nm. The total output power of the EDTFA module was 20.4 dBm and its power conversion efficiency reached 32.8%.     

Efficient thulium-doped 2-/spl mu/m germanate fiber laser

We report an efficient fiber laser operating near 2 /spl mu/m. The glass for the fiber is germanate that is highly doped with thulium. The effect of cross relaxation energy transfer between thulium ions as observed from emission spectrum of the glass samples results in the laser having a very high slope efficiency of 58% with respect to launched power. This corresponds to a quantum efficiency of 1.79, indicating that each pump photon leads to near 1.8 excited Tm/sup 3+/ ions.     

50-GHz optically injection-locked 1.55-/spl mu/m VCSELs

High-speed directly modulated diode lasers are important for optical communications and optical interconnects. In this work, we demonstrate greatly enhanced resonance frequency for vertical-cavity surface-emitting lasers, from 7 to 50 GHz, under ultrahigh injection-locking conditions. In addition, a 20-dB gain is achieved for small signal modulation below resonance frequency.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

High-power 2.3-/spl mu/m GaSb-based linear laser array

High-power 2.3-/spl mu/m In(Al)GaAsSb-GaSb type-I double quantum-well diode laser arrays were fabricated and characterized. Linear laser arrays with 19 100-/spl mu/m-wide elements on a 1-cm-long bar generated 10 W in continuous-wave (CW) mode and 18.5 W in quasi-CW mode (30 /spl mu/s/300 Hz) at a heatsink temperature of 18/spl deg/C. Array power conversion efficiency peaked at 30 A and was about 9%. Device internal efficiency was about 50%. Individual laser differential gain with respect to current was about twice as high as in InP-based laser heterostructures, demonstrating the potential of GaSb-based material system for high-power CW room-temperature laser diode arrays.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology

Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage capacitor is provided by the adjacent word line. This layout achieves the same density as the conventional double-polysilicon cell, and comparable performance is obtained using a low-resistance polycide word line. Hi-C implants in the storage region provide increased capacitance, better isolation, and reduced transient noise. Design and operation considerations for the cell and arrays are described and measured results are compared to the design values. A cell area of 34 /spl mu/m/SUP 2/ is achieved using a scaled-down n-channel FET technology with a 22.5 nm gate oxide and 1 /spl mu/m minimum mask feature size.     

Low-noise metamorphic HEMTs with reflowed 0.1-/spl mu/m T-gate

A 0.1-/spl mu/m T-gate fabricated using e-beam lithography and thermally reflow process was developed and applied to the manufacture of the low-noise metamorphic high electron-mobility transistors (MHEMTs). The T-gate developed using the thermally reflowed e-beam resist technique had a gate length of 0.1 /spl mu/m and compatible with the MHEMT fabrication process. The MHEMT manufactured demonstrates a cutoff frequency f/sub T/ of 154 GHz and a maximum frequency f/sub max/ of 300 GHz. The noise figure for the 160 /spl mu/m gate-width device is less than 1 dB and the associated gain is up to 14 dB at 18 GHz. This is the first report of a 0.1 /spl mu/m MHEMT device manufactured using the reflowed e-beam resist process for T-gate formation.     

A low-voltage folded-switching mixer in 0.18-/spl mu/m CMOS

Scaling of CMOS technologies has a great impact on analog design. The most severe consequence is the reduction of the voltage supply. In this paper, a low voltage, low power, AC-coupled folded-switching mixer with current-reuse is presented. The main advantages of the introduced mixer topology are: high voltage gain, moderate noise figure, moderate linearity, and operation at low supply voltages. Insight into the mixer operation is given by analyzing voltage gain, noise figure (NF), linearity (IIP3), and DC stability. The mixer is designed and implemented in 0.18-/spl mu/m CMOS technology with metal-insulator-metal (MIM) capacitors as an option. The active chip area is 160 /spl mu/m/spl times/200 /spl mu/m. At 2.4 GHz a single side band (SSB) noise figure of 13.9 dB, a voltage gain of 11.9 dB and an IIP3 of -3 dBm are measured at a supply voltage of 1 V and with a power consumption of only 3.2 mW. At a supply voltage of 1.8 V, an SSB noise figure of 12.9 dB, a voltage gain of 16 dB and an IIP3 of 1 dBm are measured at a power consumption of 8.1 mW.     

Recombination mechanisms in 1.3-/spl mu/m InAs quantum-dot lasers

We measure, in real units, the radiative and total current density in high performance 1.3-/spl mu/m InAs quantum-dot-laser structures. Despite very low threshold current densities, significant nonradiative recombination (/spl sim/80% of the total recombination) occurs at 300 K with an increasing fraction at higher current density and higher temperature. Two nonradiative processes are identified; the first increases approximately linearly with the radiative recombination while the second increases at a faster rate and is associated with the loss of carriers to either excited dot states or the wetting layer.     

Multifunctional characteristics of 1.5-/spl mu/m two-section amplifier-modulator-detector SOA

The multifunctional characterization of a two-section amplifier-modulator-detector semiconductor optical amplifier (AMD-SOA) is presented. Detectivity is analyzed in terms of bandwidth and responsivity while modulation properties are characterized by temporal response and extinction ratio. Receiver sensitivities of -26 dBm at 155 Mb/s and -19.5 dBm at 622 Mb/s and error-free signal modulation/transmission with simultaneous 10 dB amplification at 622 Mb/s with a 2/sup 23/-1 PRBS signal are reported. This device could find application as transparent add-drop node in photonic packet-switched optical ring networks.