On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs     

Demonstration of photonically controlled GaAs digital/MMIC for RFoptical links

We report design, fabrication, and test of a monolithic GaAs optoelectronic integrated circuit (OEIC) implementing a broad-band optically driven digital/analog radio frequency (RF) interface. The integrated circuit (IC) was fabricated using a foundry-compatible enhancement/depletion metal-semiconductor field-effect transistor (MESFET) process with no added lithography steps. A single optical fiber carries externally amplitude modulated 0.85-μm light to the on-chip GaAs metal-semiconductor-metal interdigitated photodetector. RF as well as simultaneous digital information encoded at up to 10 Mb/s using a novel waveform set is transmitted over the fiber. The serial digital data is self-clocked into on-chip registers to control the RF signal chain, which includes a three-bit digital attenuator. The circuit operates in an asynchronous mode to detect digital and RF on the single optical-fiber input, control RF level, and transmit the 2-8-GHz RF to the IC's electrical output. Measurements characterizing the RF and digital performance of the IC as well as a demonstration of the full optoelectronic mixed-mode functioning of the IC are presented     

An analysis of small-signal source-body resistance effect on RF MOSFETs for low-cost system-on-chip (SoC) applications

In this paper, we demonstrate a comprehensive analysis of small-signal source-body resistance (R/sub sb/) effect on the RF performances of RF MOSFETs for low-cost system-on-chip (SoC) applications for the first time. Our results show that for RF MOSFETs, both the kink phenomena of S/sub 11/ and S/sub 22/ become more obscure as reverse body bias (V/sub B/) increases due to the decrease of transconductance (g/sub m/). In addition, an increase of source-body spacing enhances both the kink phenomena of S/sub 11/ and S/sub 22/, but deteriorates the current-gain cut-off frequency (f/sub T/), maximum oscillation frequency (f/sub MAX/), and RF noise and power performances due to the increase of R/sub sb/ of the devices. Analytical formulas are derived to explain the kink phenomena of S/sub 11/ and S/sub 22/, and to explain why increasing R/sub sb/ leads to a reduction of equivalent substrate resistance R/sub sub/, or worse f/sub T/, f/sub MAX/, and RF noise performances of the devices. The present analyzes enable RF engineers to understand the S-parameters, noise parameters, and power performances of RF MOSFETs more deeply, and hence are helpful for them to optimize the layout of MOSFETs and to create a fully scalable RF CMOS model for SoC applications.     

CMOS反相器高功率微波扰乱效应分析

通过对CMOS数字电路器件及RF脉冲扰乱效应的模拟分析,比较了注入不同频率与功率的RF扰乱脉冲时对CMOS反相器输出逻辑电平扰乱甚至翻转的效应过程。     

RF figures-of-merit for process optimization

Today, transistor y-parameters are routinely being measured for the determination of the current-gain cut-off frequency f/sub T/ and the maximum oscillation frequency f/sub max/. In this paper, it is shown that a much wider use of y-parameter measurements can be made for the RF characterization of transistors. A method is presented to determine the small-signal behavior of actual RF circuit-blocks from the measurements of the y-parameters of the individual circuit components. This is applied to define additional RF figures-of-merit for basic building blocks of analogue and digital RF circuits. No equivalent transistor circuit or compact-model parameters are needed, which is important for giving quick feedback to process developers. This approach is illustrated on three basic RF circuit blocks using bipolar transistors.     

Low‐Cost High‐Performance TDD Synchronizer for WiBro RF Repeater

WiBro radio frequency (RF) repeater is used for solving the problem of partial shadow areas in the wireless communication field that uses time‐division duplexing (TDD) mode. In this paper, a method to efficiently generate TDD signals for WiBro RF repeater is proposed and its digital circuit is implemented. A TDD signal is detected from RF signals transmitted/received to/from RF repeater and then inputted again into the RF repeater, so that it can operate normally. First, the envelope of downlink signals is detected and then clamped to extract the basic form of a TDD signal using an operational amplifier circuit. Next, the TDD signal is generated by restoring and filtering the shape which has been distorted by the wireless channel. The algorithm and system to acquire TDD signal are developed with a goal to have simple but powerful functions with as little cost as possible. The proposed method is implemented as an RF‐digital integrated system and verified through the experiments under the same condition as actual WiBro service environment.     

一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路

提出了一种适用于无源超高频射频识别标签的低电压低功耗射频/模拟前端电路.通过引入一个使用亚阈值技术的基准源,电路实现了温度补偿,从而使得系统时钟在～40～100℃的范围内保持稳定.在模块设计中,提出了一些新的电路结构来降低系统功耗,其中包括一种零静态功耗的上电复位电路和一种新的稳压电路.该射频/模拟前端电路采用不带肖特基二极管0.18μm CMOS EEP-ROM工艺流片实现,它与数字基带、EEPROM一起实现了一个完整的标签芯片.测试结果表明,该芯片的最低电源电压要求为0.75V.在该最低电压下,射频/模拟前端电路的总电流为4.6μA.     

基于PLL技术的射频信号数字调谐系统的分析设计

本文以锁相环PLL（Phase—LockedLoops）技术为理论基础，通过对射频信号接收机本振（LO，Local Oscnlator），即数字频率调谐部分的分析，提出了一种对低功耗BICMOS数字频率调谐电路的分析设计方法，详细分析了它的工作原理，并给出了具体电路，仿真波形以及分析数据。该电路的主要特点是采用可编程的分频器调谐频率分频比，从而使PLL系统自动锁定在想要的频率电压上，以此来控制压控振荡器VCO（Voltage Controlled Oscillator）经再次分频后形成L0输出。     

硅衬底RF集成电路中螺旋电感的建模和分析

对硅衬底RF集成电路中的螺旋电感进行电磁场建模,考虑了衬底损耗效应,并通过电路分析和网络分析技术得到了二端口简化电感模型.该模型在特定的截止频率以下可提供可靠的电路系统仿真.利用该模型分析了硅衬底的损耗对螺旋电感品质因素(Q)的影响.     

Design Considerations for High Performance RF Cores Based on Process Variation Study

RF circuits play a vital role in high data rate communication systems. Although at the design stage several considerations are made to ensure that the designed circuit functions as per desired specifications, the effect of process variations on the circuit’s performance is less understood. The parametric variations arising from the various stages of fabrication play a significant role in determining the device characteristics. In this paper, in order to analyze the effect of process variations, we consider a bottom–up approach beginning at the component level for active and passive elements and then move to the circuit level in an RF circuit consisting of both analog and digital components. We take Low Noise Amplifier (LNA) and a Phase Frequency Detector (PFD) which is one of the important building blocks of a Phase Locked Loop (PLL) as case studies for circuit level analysis. In the case of LNA, the performance is analyzed in terms of the S-parameters, gain and Noise Factor on different topologies and for a PFD, an analytical model is developed and the analysis is carried out using the Monte Carlo method to verify the robustness of the circuit elements towards phase noise. Our hierarchical multi-phase analysis technique is shown to provide valuable insights into designing robust RF circuits.     

RF-LDMOS器件宏模型研究

射频器件模型是射频电路仿真的基本要素之一。为了解决射频横向双扩散金属氧化物半导体晶体管（RF-LDMOS）缺乏准确SPICE模型的问题。此处提出了一种适用于带封装结构的RF-LDMOS器件宏模型建模及提模方法,并采用MBP软件进行验证分析。结果表明该宏模型建模方法能够很好的实现数据拟合,直流特性和射频特性的误差均在5%范围内,能够准确地反映器件的电学特性。     

Frequency-independent equivalent-circuit model for on-chip spiral inductors

A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.     

Broadband Macromodels for Retarded Partial Element Equivalent Circuit (rPEEC) Method

The partial element equivalent circuit (PEEC) method is, nowadays, widely used in electromagnetic compatibility and signal integrity problems in both the time and frequency domains. Similar to other integral-equation-based techniques, its time domain implementation may suffer from late time instabilities, especially when considering delays [(Lp,P,R,tau)PEEC] (rPEEC). The cause of the instabilities may be either the numerical technique used for the time integration or problems created by the discrete representation of the electromagnetic continuous problem. In this paper, we concentrate on the latter and show that frequency dispersion plays an important role and must be taken into account in order to preserve accuracy and mitigate instabilities issues. An enhanced formulation of the PEEC method is presented that is based on a more accurate computation of partial elements describing the electric and magnetic field couplings; broadband macromodels are generated incorporating the frequency dependence of such elements, thus, allowing us to obtain better stability properties of the resulting (Lp,P,R,tau)PEEC model. The proposed equivalent circuits resemble those of the standard PEEC formulation but are able to capture the dispersion that, when neglected, might contribute to inaccuracies and late time instabilities     

Electronic prognostics – A case study using global positioning system (GPS)

Prognostic health management (PHM) of electronic systems presents challenges traditionally viewed as either insurmountable or otherwise not worth the cost of pursuit. Recent changes in weapons platform acquisition and support requirements have spurred renewed interest in electronics PHM, revealing possible applications, accessible data sources, and previously unexplored predictive techniques. The approach, development, and validation of electronic prognostics for a radio frequency (RF) system are discussed in this paper. Conventional PHM concepts are refined to develop a three-tier failure mode and effects analysis (FMEA). The proposed method identifies prognostic features by performing device, circuit, and system-level modeling. Accelerated failure testing validates the identified prognostic features. The results of the accelerated failure tests accurately predict the remaining useful life of a commercial off the shelf (COTS) GPS receiver to within ±5 thermal cycles. The solution has applicability to a broad class of mixed digital/analog circuitry, including radar and software defined radio.     

A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

A simple model has been developed to characterize electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance of fast and slow logic devices in such a circuit.     

An architecture for self-test of a wireless communication systemusing sampled IQ modulation and boundary scan

An architecture for system-level self-test of a wireless communication transceiver integrates the functional (parametric) self-test of the radio frequency subsystem, and the structural self-test of the digital subsystem. The digital subsystem is tested using extensions of the IEEE 1149.1 boundary scan standard to verify connections within circuit boards and between boards. The RF subsystem is tested using a loopback connection between the RF transmitter and receiver. An RF parametric self-test is performed using a digitally modulated signal (as opposed to a sinusoidal tone) as the test stimulus, and using samples from the receiver digitizer as test data. This loopback test scheme imposes a relatively small overhead on the RF system design     

L波段集成自检源小型化多通道前端

L波段射频系统的前端模块,在完成放大滤波功能的基础上,还需要具有产生自检信号的功能,以及与上位机进行通信的能力。为了适应现代社会对设备功能完备、体积小、质量轻的要求,通过选用小型集成化跳频源,将数字控制、接口电路与微波控制电路相集成,将自检功分电路与微波控制电路集成,研制出一款集成自检源的多通道射频前端。在保证原有射频前端放大滤波功能、产生自检信号功能、与上位机进行通信功能的基础上,大幅度地减小了射频前端的体积与质量。通过实物制作与测试,验证了上述设计方法在保证多通道射频前端功能完整性的情况下可以大幅度减小整体模块的体积、减轻模块的质量。     

一种低功耗数字式人工关节无线监视系统

提出了一种由压电陶瓷和射频电路供电的低功耗数字式人工关节无线监视系统。该系统监视人工关节的工作情况,通过传感器得到人工关节的异常压力、磨损情况等数据,经过数模转换、存储后,通过射频信号,以无线方式发送至体外电路。对系统的各个部分进行了详细描述。部分电路已经得到流片验证或仿真,测试结果符合系统要求。     

RF and AMS

The paper shows four basic circuit functions which are RF transceiver, AMS, power amplifier (PA) and power management (PM), and digital signal processor (DSP). In this article, the authors emphasize the first three circuit functions, which drive analog and RF technology needs. Each of those three major parts in a RF front-end for a wireless system are discussed in a separate section with special emphasis on the device needs and technology choices for those blocks and with main focus on the frequency range from 0.8 to 10 GHz. A section on millimeter wave circuits and devices cover device and technology integration issues for applications in the frequency range starting from 10-100 GHz. Finally, we discuss the evolution of technology choices, integration issues, and potentially new emerging devices, all within the time-frame for the 2003 ITRS roadmap (2003-2018).     

A New Automatic Compensation Network for System‐on‐Chip Transceivers

This paper proposes a new automatic compensation network (ACN) for a system‐on‐chip (SoC) transceiver. We built a 5 GHz low noise amplifier (LNA) with an on‐chip ACN using 0.18 µm SiGe technology. This network is extremely useful for today's radio frequency (RF) integrated circuit devices in a complete RF transceiver environment. The network comprises an RF design‐for‐testability (DFT) circuit, capacitor mirror banks, and a digital signal processor. The RF DFT circuit consists of a test amplifier and RF peak detectors. The RF DFT circuit helps the network to provide DC output voltages, which makes the compensation network automatic. The proposed technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance, gain, and noise figure using the developed mathematical equations. The ACN automatically adjusts the performance of the 5 GHz LNA with the processor in the SoC transceiver when the LNA goes out of the normal range of operation. The ACN compensates abnormal operation due to unusual thermal variation or unusual process variation. The ACN is simple, inexpensive and suitable for a complete RF transceiver environment.