大幅度CCD输出信号降噪的相关双取样电路

电荷耦合器件(CCD)的输出信号构成复杂,包含有典型的KTC、1/f等类型的噪声,需要进行专门处理后才能获得与入射光信号相对应的高信噪比信号。文章针对具有较大幅度的CCD输出信号,采用宽电压工作的独立运放满足幅度较大的信号处理要求;通过在同一个运算放大器上实现噪声保持及信号采样的形式,消除了不同通道增益差异对信号的影响,获得了较高线性度的信号处理效果;同时结合CCD驱动器的设计,获取相关双取样技术所需的采样及保持脉冲信号,增强了采样与CCD输出信号间的关联程度,从而进一步提高了相关双取样技术消除CCD噪声的效果。采用这种信号处理电路后,将原来噪声处理的水平从约22 mV提高到了约1 mV,并且在一种精密的位移测量系统中得到应用,最后就具体电路设计的难点及注意事项进行了阐述。     

CCD输出信号的低噪声处理电路研究

本文针对电荷耦合器件（CCD）输出信号需要的低噪声处理要求研究了一种高增益、低噪声的信号处理电路,指出了电路的设计难点及注意事项。     

CCD电荷转换因子通用测试方法研究

通过分析电荷耦合器件(CCD)图像传感器光电转换、电荷转移、电荷输出的工作原理,提出了一种通用高效的电荷转换因子(CVF)测试方法。该方法采用在CCD感光区域施加直流偏压,水平区施加连续转移的驱动时序的方式,使CCD光敏区以电荷溢出方式往水平区转移电荷,水平区以固定频率不间断转移输出电荷包,从而让CCD输出强度恒定的响应信号;然后通过复位漏电流与输出信号强度的对应关系计算出CCD器件的CVF值。根据该方法的原理设计了一种适应各种CCD器件的通用测试装置,并对多款CCD进行测试验证。结果表明,该方法有效提高了CCD电荷转换因子的测试效率、测试精度和稳定性。     

用三种类型P阱结构制成的电荷耦合器件传感器

本文描述了适用于16.9mm(2/3英寸)规格的一种488×590元列间转移电荷耦合器件(CCD)传感器。这种传感器采用了三种 p 阱(浅层阱、中层阱和深层阱)来抑制起晕和弥散。浅层 p 阱组合有光电二极管,并且为抑制起晕而完全耗尽;中层p 阱做 CCD 移位寄存器,并且为抑制弥散而完全耗尽;深层 p 阱做输出电路,并为 MOS 管的稳定操作而不完全耗尽。在10%的垂直高度光照时,起晕信号和在波长为550nm 时的光照信号一样小,为-73dB。此外,这种传感器采用 n~+-n~--p 光电二极管,以减少光谱响应随信号电荷存储的变化。     

大动态高灵敏1024×1024 EMCCD研制

随着硅材料质量的提升和半导体工艺技术的发展，低温制冷下电荷耦合器件(CCD)的暗电流已经可以忽略，此时放大器成了主要的噪声源，限制了对微弱信号的检测。采用电子倍增技术，通过对电荷包在进入输出节点前进行放大，可有效抑制放大器的噪声。然而，电荷包放大后容易饱和，会限制器件的动态范围。本研究采用浮置栅放大器对电荷包进行无损检测。根据检测结果，大的电荷包直接输出，小的电荷包通过电子倍增放大后再输出，获得高灵敏度的同时兼顾了大的动态范围。根据实际测试结构，在10^-4 Lx光照下得到了良好的微光成像效果，同时动态范围可达15万倍。     

1024×1024元帧转移纵向抗晕CCD图像传感器

帧转移电荷耦合器件(FTCCD)主要应用于可见光信号探测,其在强光应用场合容易出现光晕现象。针对该问题,研制了帧转移纵向抗晕CCD图像传感器,该器件阵列规模为1 024×1 024元,像素尺寸为12μm×12μm。为了实现纵向抗晕功能,采用了n型埋沟-鞍形p阱-n型衬底结构,纵向抗晕倍数为200倍,器件满阱电子数为大于等于200 ke^-,读出噪声小于等于80 e^-,动态范围大于等于2 000∶1。     

横向抗弥散多光谱TDI CCD图像传感器

时间延迟积分电荷耦合器件(TDI CCD)主要应用于弱光信号探测,其在强光应用场合容易出现弥散现象。针对该问题,研制了横向抗弥散多光谱TDI CCD图像传感器。该器件包含四个多光谱段(B1～B4区),有效像元数为3 072元,像元尺寸为28μm×28μm。大像元可以在弱光环境下提供良好的光谱区分能力,通过滤光片可获得蓝光、绿光、红光和近红外波段的图像。为了减小抗弥散对器件满阱电子数的不利影响,采用了紧凑的抗弥散结构,仅占像元面积的7.1%。器件满阱电子数为500ke-,抗弥散能力为100倍,读出噪声小于等于70e-,动态范围大于等于7143∶1。     

Ge量级大满阱容量脉冲频率调制电路设计

本文对一种提高红外焦平面读出电路满阱电荷容量的方法进行了研究。采用了基于脉冲频率调制结构的单元电路,与传统电路相比满阱电荷容量提高了1～2个量级。本文对该像元的电路结构、工作原理与信号误差进行了分析。单元电路前端的调制器将光电流信号调制成一系列固定频率的脉冲信号,计数器记录脉冲个数,脉冲个数与输入的光电流信号成正比,通过脉冲个数来表征光电流的信号量。使用0.35?m 2P4M工艺进行了电路设计与验证。通过测试结果表明,最大电荷容量达到了3.5Ge,每个电荷包的电荷量为5.46 ke,该方法的电荷容量提高了2个量级。     

双开关电荷采样放大器

电荷放大器是高阻抗电荷源器件普遍采用的前置电路,电荷采样放大器保持了电荷放大器功能,同时可以消除电荷放大器直流漂移导致的输出饱和,但是单开关的电荷采样放大器是不稳定电路。文中分析了电荷采样放大器的工作原理,提出了双开关电荷采样放大器,该电路不自激振荡,无输出饱和,其输出可以直接作为Ａ／Ｄ转换电路的输入。     

埋沟CCD器件电荷处理容量的二维数值模拟

借助于二维器件模拟软件PISCES-IIB,通过在某相CCD电极下的耗尽区注入数量可控的电子电荷,对埋沟CCD器件电荷容量进行了定量分析。采用此方法对一种沟道宽度为7μm的CCD信道电荷容量进行了瞬态模拟,对不同结深、不同沟道掺杂浓度对CCD电荷容量的影响进行了讨论。得到了此结构工艺参数的初步优化结果,即CCD沟道表面掺杂浓度为结深为1 μm时,埋沟CCD的电荷容量可达文章提出的方法适用于其他CCD单元结构电荷容量的模拟。     

Charge handling capacity in charge coupled devices

In analog signal processing applications, the charge handling capacity of a charge coupled device (CCD) is an important parameter that determines the dynamic range. In this paper, approximate expressions for the signal handling capacity for surface-channel and buried-channel CCD's are derived and compared. The upper limit for the buried-channel charge capacity is imposed by the onset of surface electron accumulation.     

面向深空探测的CCD多像元合并设计与验证

在火星矿物光谱分析仪中采用模拟4像元合并,可以使仪器应对深空探测中的复杂环境,从而达到高信噪比与高动态范围的要求。提出了一种新型CDD片上2×2像元合并的驱动方法,并验证了其输出的合理性。针对e2v CCD 47-20芯片,研究了CCD结构并设计了行方向与列方向2像元合并的方法,使之可以通过FPGA控制生成驱动波形。基于CCD片上放大器的结构,通过仿真其行方向两元输出模拟信号模型,得到了四阶梯模型。均匀光照射实验结果表明,得到的4-binning模式下CCD输出信号与仿真结果一致,验证了理论的正确性。其输出电压在600 mV以下范围内表现出了良好的线性变化趋势,证明该方案的合并结果是精确可靠的。     

A CCD video delay line with charge-integrating amplifier

The authors describe a charge coupled device (CCD) sense amplifier in a video delay line which overcomes the major limitations of conventional floating diffusion amplifier (FDA) technology, such as limited output voltage and operating temperature range. These advances are implemented with a switched-capacitor integrator (SCI) using an op amp with a newly developed output stage in a CMOS-CCD process. This circuit is effected within the constraints of 5-V operation by using negative pulses to reach the low channel potential of the CCD in the pinning region in the final gate of the CCD. The chip operates with 14.3-MHz clock and 5-V power supply, and can process a 1.0-V_p-p signal voltage under 1% distortion, and under 4% gain variation from -20 to 70°C     

High-speed charge transfer sense amplifier for 0.5 V DRAM array applications

A new high-speed charge transfer sense amplifier scheme is proposed for 0.5 V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts.     

A high performance sense amplifier for a 5 V dynamic RAM

Increasing dynamic RAM cell density and the use of a single low-voltage power supply have made it mandatory to store the full power supply voltage in the cell and to be able to detect smaller signals reliably with the initial sense amplifier. The authors present a circuit design approach that restores the cell to a full V/SUB DD/ `1' level, preamplifies the initial charge imbalance before sensing by conventional techniques, and is used in the Fairchild 64K design. Design requirements and a detailed analysis of the amplifier are presented along with simulated results, followed by performance data. The circuit analysis shows how the key design parameters should be chosen and the effects of clock timing variations on the performance of the sense amplifier.     

Design and operation of a floating gate amplifier

A unique amplifier configuration is examined that fully exploits the intrinsically high signal-to-noise performance of charge-coupled devices (CCD's). In this amplifier, the signal charge is detected with a conducting `floating gate' embedded in the oxide between a bias electrode and the silicon substrate. The change of voltage on the floating gate produced by the signal charge in the CCD channel is then used to modulate the current flow in a metal-oxide-semiconductor (MOS) transistor. The signal charge remains isolated and can be moved downstream in the CCD channel; thus, it can be detected again by other similar structures. Computer analysis, test structure design, and experimental results of a floating gate amplifier (FGA) are presented.     

An in-probe receiver amplifier with 3 dB noise figure and 50 dB dynamic range for medical ultrasound imaging using CMUTs

This paper presents the design and measurements of an in-probe receiver amplifier for ultrasound imaging applications using a capacitive micromachined ultrasonic transducer (CMUT). In such applications, the noise and the dynamic range play very important roles, as the former dictates the minimum input signal level and the latter defines the maximum input signal level that can be applied to a system. This work concentrates on both of these specifications. The amplifier consists of a transimpedance amplifier followed by a voltage gain stage implemented using a current feedback amplifier. It is designed and fabricated using a 180 nm CMOS process. A noise figure of 3 dB is measured for a CMUT model with 10–30 MHz frequency range. The amplifier shows a dynamic range of 50 dB with 0.8 % total harmonic distortion for the full scale input current of 7 µA peak-to-peak.     

Charge-coupled device structures for VLSI memories

High-performance CCD's which can operate at the scaled voltage levels and geometry sizes projected for VLSI memory will require the storage, transfer, and detection of very small charge packets (≤25 000 electrons). The scaling requirements for such CCD structures are shown to be more complex than MOS scaling laws. The device physics of CCD structures which can meet these performance requirements are discussed and related to material and technology problems which must be overcome. For a given area, an enhanced-capacity implant technique is used to increase the storage capacity. A new detection scheme using a bipolar charge amplification allows up to an order of magnitude increase in output sensitivity. Transient subthreshold measurements show that very small interelectrode barriers may exist at low clock voltage overdrive which severely limit CCD transfer efficiency at small geometries.     

热载流子效应对CCD片上放大器寿命的影响

针对CCD片上放大器的寿命进行了研究。通过设计独立的MOSFET,使用衬底电流模型进行热载流子效应分析,研究其特性参数Gm退化量与退化时间关系,由此评价组成CCD片上放大器的寿命。研究结果表明,CCD片上放大器寿命随着栅长的减小而降低,制作LDD结构可提高CCD片上放大器寿命。