Time dependent breakdown of ultrathin gate oxide

Time dependent dielectric breakdown (TDDB) of ultrathin gate oxide (<40 Å) was measured for a wide range of oxide fields (3.4<|E_ox|<10.3 MV/cm) at various temperatures (100⩽T⩽342°C). It was found that TDDB of ultrathin oxide follows the E model. It was also found that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. Below 4.8 MV/cm, TDDB t₅₀ of intrinsic oxide increased above the value predicted by the E model obtained for fields >4.8 MV/cm. The TDDB activation energy for this type of gate oxide was found to have linear dependence on oxide field. In addition, we found that γ (the field acceleration parameter) decreases with increasing temperature. Furthermore, it was found that testing at high temperatures (up to 342°C) and low electric field values did not introduce new gate oxide failure mechanism. It is also shown that TDDB data obtained at very high temperature (342°C) and low fields can be used to generate TDDB model at lower temperatures and low fields. Our results (an enthalpy of activation of 1.98 eV and dipole moment of 12.3 eÅ) are in complete agreement with previous results by McPherson and Mogul. Additionally, it was found that TDDB is exponentially dependent on the gate voltage     

The statistical distribution of percolation current for soft breakdown in ultrathin gate oxide

Soft breakdown in ultrathin gate oxide has been studied using constant voltage stressing. The behavior of current increments resulting from a number of soft breakdown events has been characterized by statistical distribution. It is shown that the distribution of the current increment follows Weibull distribution rather than log normal distribution. The newly established Weibull slope is shown to be independent of the stressed voltage in the range investigated between 4.5 and 5.1 V. The temperature effect study shows that the Weibull slope reduces with increasing testing temperature. Furthermore, a strong dependence of the Weibull slope on the oxide thickness has been found. These observations can be explained well by geometrical configurations of the percolation path.     

Micro breakdown in small-area ultrathin gate oxides

The purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness t/sub OX/=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1 mA or smaller than 100 pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40 pA at V/sub G/=+2 V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using a new original model of double trap-assisted tunneling (D-TAT) developed ad hoc.     

On physical models for gate oxide breakdown

Electrical breakdown of thin (32-nm) SiO2films subjected to constant-current stressing is studied. By studying the effects of reversing the polarity of the constant-current bias and the effects of thermal annealing on the charge-to-breakdown it is determined that electrical breakdown of SiO2is not caused by the widely-cited accumulation of trapped electrons. Rather it is caused by the buildup of positive charges near the cathode at localized areas. The positive charges are not mobile ions but exhibit many characteristics of trapped holes. We conclude that electrical breakdown in SiO2is caused by the accumulation of holes, generated by impact ionization in the oxide.     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Experimental evidence of T/sub BD/ power-law for voltage dependence of oxide breakdown in ultrathin gate oxides

In this paper, we present experimental evidence on the voltage-dependence of the voltage acceleration factors observed on ultrathin oxides from 5 nm down to /spl sim/1 nm over a wide range of voltages from /spl sim/2 V to 6 V. Two independent experimental approaches, area scaling method and long-term stress, are used to investigate this phenomenon. We show the exponential law with a constant voltage-acceleration factor violates the widely accepted fundamental breakdown property of Poisson random statistics while the voltage-dependent voltage acceleration described by an empirical power-law relation preserves this well-known property. The apparent thickness-dependence of voltage acceleration factors measured in different voltage ranges can be nicely understood and unified with these independent experimental results in the scenario of a voltage-driven breakdown. In the framework of the critical defect density and defect generation rate for charge-to-breakdown, we explore the possible explanation of increasing voltage acceleration factors at reduced voltage by assuming a geometric model for the critical defect density.     

Circuit implications of gate oxide breakdown

A model for the oxide breakdown (BD) current–voltage (I–V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains.     

Are soft breakdown and hard breakdown of ultrathin gate oxidesactually different failure mechanisms?

By means of a statistical analysis, the soft breakdown and hard breakdown of thin gate SiO₂ films in MOS devices are shown to have a common physical origin. Being triggered by identical microscopic defects, these breakdown modes can be actually considered to be the same failure mechanism. In particular, it is shown that the soft breakdown conduction path is not precursor of the final hard breakdown event, which generally appears at a different spatial location. The huge differences between the soft and hard post-breakdown current-voltage (I-V) characteristics are attributed to differences in the breakdown spot area and to point contact energy funneling effects     

Role of hole fluence in gate oxide breakdown

A simple model which links the primary hole and Fowler-Nordheim (FN) electron injections to oxide breakdown is established and the calculation based on this model is in good agreement with our experiments. When the sum of the active trap density D^pri due to primary hole injection and the active trap density Dⁿ due to FN electron injection reaches a critical value D_cri, the oxide breaks down. The hole is two orders of magnitude more effective than FN electron in causing breakdown. These new findings are imperative in predicting oxide reliability and device lifetime     

Through-the-gate-implanted ultrathin gate oxide MOSFET's withcorner parasitics-free shallow-trench-isolation

We have realized direct-tunneling (DT) gate oxide (1.6 nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a corner parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel-doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench corner parasitics are eliminated by the advanced process architecture without increasing process complexity. Fully functional direct-tunneling oxide MOSFET's with excellent electrical characteristics confirm the feasibility of this novel approach     

Physical analysis of hard and soft breakdown failures in ultrathin gate oxides

The physical analysis of the ultrathin gate oxides (33 and 25 Å) after the electrical stressing, under constant voltage stress, reveals that the damage is not only limited to the oxide layer, but also to the entire gate structure. The hard breakdown failure makes catastrophic damage to the structure, whereas the analysis of soft breakdown failure reveals many of the hidden damages in the device structure. In Ti-silicided structures, the predominant failure mechanism is Ti migration to form a leakage path, as well as localized re-crystallisation of poly-Si or Si substrate near to the gate oxide. Co migration is so far not seen in Co-silicided devices. However, even for the very low current compliance levels and devices which do not show any electrical degradation after the SBD stress, localized epitaxy formation in the gate or Si substrate is observed, which could be a reliability concern.     

Investigation of gate oxide breakdown in CMOS integrated circuits

Investigation of gate oxide breakdown in CMOS integrated circuits, aimed at establishing its dependence on substrate doping (type and level) and its acceleration by an electric field, has been performed in this paper. In order to do this, time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric-breakdown (constant-voltage-stressed I-t) tests were carried out and the gate oxide breakdown histograms and electric field acceleration factor were determined and discussed in detail.     

Substrate bias dependence of breakdown progression in ultrathin oxide pMOSFETs

Negative substrate bias-enhanced oxide breakdown (BD) progression in ultrathin oxide (1.4 nm) pMOS is observed. The enhanced progression is attributed to the increase of hole-stress current resulting from BD-induced, channel-carrier heating. The carrier temperature extracted from the spectral distribution of hot-carrier luminescence is around 1300 K. The substrate bias dependence of post-BD hole-tunneling current is confirmed from measurement and calculation. The observed phenomenon is particularly significant to ultrathin gate oxide reliability in floating substrate (SOI) and forward-biased substrate devices.     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics

Prior to any attempt to model a charge transport mechanism, a precise knowledge of the parameters on which the current depends is essential. In this work, the soft breakdown (SBD) failure mode of ultrathin (3-5 nm) SiO₂ layers in polysilicon-oxide-semiconductor structures is investigated. This conduction regime is characterized by a large leakage current and by multilevel current fluctuations, both at low applied voltages. In order to obtain a general picture of SBD, room-temperature current-voltage (I-V) measurements have been performed on samples with different gate areas, oxide thicknesses and substrate types. An astounding matching between some of these I-V characteristics has been found. The obtained results and the comparison with the final breakdown regime suggest that the current flow through a SBD spot is largely influenced by its atomic-scale dimensions as occurs in a point contact configuration. Experimental data are also presented which demonstrate that specific current fluctuations can be ascribed to a blocking behavior of unstable SBD conduction channels     

Improved method for the oxide thickness extraction in MOSstructures with ultrathin gate dielectrics

An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique and of Vincent's method is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm to 1.8 nm     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

Localized oxide degradation in ultrathin gate dielectric and its statistical analysis

Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibull's statistics for multiple degraded spots.     

Field and temperature dependence of TDDB of ultrathin gate oxide

The results of an investigation of time-dependent breakdown (TDDB) of intrinsic ultrathin gate oxide are presented for a wide range of oxide fields 4.6ox<10.4 MV/cm at elevated temperatures. It was found that TDDB of ultrathin oxide follows the E model down to 4.6 MV/cm. The data show that TDDB t₅₀ starts deviating from the 1/E model for fields below 7.2 MV/cm. The data also show that the TDDB activation energy for this type of gate oxide is linearly dependent on oxide field. In addition, we show that the field acceleration parameter γ decreases as temperature increases