A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet

1000BASE-T Gigabit Ethernet employs eight-state 4-dimensional trellis-coded modulation to achieve robust 1-Gb/s transmission over four pairs of Category-5 copper cabling. This paper compares several postcursor equalization and trellis decoding algorithms with respect to performance, hardware complexity, and critical path. It is shown that parallel decision-feedback decoders (PDFD) offer the best tradeoff. The example of a 14-tap PDFD, however, shows that it is challenging to meet the required throughput of 1 Gb/s using current standard-cell CMOS technology. A modified approach is proposed which uses decision-feedback prefilters followed by a one-tap PDFD. This considerably reduces hardware complexity and improves the throughput while still meeting the bit-error-rate requirement. The critical path is further reduced by employing a look-ahead technique. The proposed joint equalizer and trellis decoder architecture has been implemented in 3.3-V 0.25-/spl mu/m standard-cell CMOS process. It achieves a throughput of 1 Gb/s with a 125 MHz clock. Compared to a 14-tap PDFD, the design improves both gate count and throughput by a factor of two, while suffering only from a 1.3-dB performance degradation.     

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.     

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing Reduced Latency DRAM (RLDRAM) II and Quad Data Rate (QDR) II SRAM memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8 Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.     

Pulse amplitude-modulated time-based interface for off-chip interconnect

An increased number of bits pulse amplitude-modulated differential-time signalling interface for off-chip interconnect is introduced in this article by combining the differential time signalling (DTS) technique with the pulse amplitude-modulation (PAM) approach. Applying the PAM to the DTS-transmitted signal increases the total number of the transmitted bits per symbol while maintaining the transmitted signal bandwidth. 4-bit 6 Gb/s DTS serial link has been designed and simulated using 65 nm CMOS mixed signal technology. 5-bit 7.5 Gb/s and 6-bit 9 Gb/s amplitude-modulated DTS serial links have been designed, simulated and compared to the 6 Gb/s DTS serial link. The three serial links use 1.5 Gb/s as input clock signal. In the amplitude-modulated DTS-transmitted signal, the rising and falling edges of the input clock signal are modulated in time as well as the transmitted signal amplitude is modulated. A reference clock pulse is generated from the input clock signal and embedded on the transmitted signal to be used as reference timing at the receiver circuit. The design details of the designed links are presented in the article. The 9 Gb/s link uses a 60 cm 4003C Rogers substrate as a transmission channel. The transmitted signal spectrum is presented and compared for the three designed links. The total power consumption of the 9 Gb/s amplitude-modulated DTS interface is less than 25 mW.     

A High-Speed Hardware Architecture for Universal Message Authentication Code

We present an architecture level optimization technique called divide-and-concatenate based on two observations: 1) the area of an array multiplier and its associated data path decreases quadratically and their delay decreases linearly as their operand size is reduced and 2) in universal hash functions and their associated message authentication codes, two one-way hash functions are equivalent if they have the same collision probability property. In the proposed approach, we divide a$2w$-bit data path (with collision probability$2^-2w$) into two$w$-bit data paths (each with collision probability$2^-w$) and concatenate their results to construct an equivalent$2w$-bit data path (with a collision probability$2^-2w$). We applied this technique on NH universal hash, a universal hash function that uses multiplications and additions. We implemented the straightforward 32-bit pipelined NH universal hash data path and the divide-and-concatenate architecture that uses four equivalent 8-bit divide-and-concatenate NH universal hash data paths on a Xilinx Virtex II XC2VP7-7 field programmable gate array (FPGA) device. This divide-and-concatenate architecture yielded a 94% increase in throughput with only 40% hardware overhead. Finally, the implementation of universal message authentication code (UMAC) with collision probability$2^-32$using the divide-and-concatenate NH hash as a building block yielded a throughput of 79.2 Gb/s with only 3840 Virtex II XC2VP7-7 FPGA slices.     

一种混合结构高速LDPC编码器的FPGA实现

分析了准循环低密度奇偶校验码生成矩阵的结构特点,讨论了硬件可实现的三种常见编码器结构,提出了一种混合结构的FPGA实现方法。通过利用循环矩阵的结构特性,增加少量硬件开销,就可以实现编码器高速编码,满足高速通信需求,吞吐量达1.36Gb/s。     

基于Interlaken协议的高速数据流接口设计与性能分析

目前,高速网络处理系统的板级互连带宽达到了40G比特速率级,这对网络处理系统的处理速度和吞吐量提出了极大的挑战。为解决核心路由器40 Gb/sPOS线路接口板中器件间的高速数据交互难题,采用Interlaken协议对高速数据流接口设计方法进行了研究,利用高端FPGA的高速通道和IP核设计技术,完成了链路层处理芯片与转发...     

Cost‐Effective Transition to 40 Gb/s Line Rate Using the Existing 10 Gb/s‐Based DWDM Infrastructure

In this paper, we propose and demonstrate a cost‐effective technique to upgrade the capacity of dense wavelength division multiplexing (DWDM) networks to a 40 Gb/s line rate using the existing 10 Gb/s‐based infrastructure. To accommodate 40 Gb/s over the link optimized for 10 Gb/s, we propose applying a combination of super‐FEC, carrier‐suppressed return‐to‐zero, and pre‐emphasis to the 40 Gb/s transponder. The transmission of 40 Gb/s DWDM channels over existing 10 Gb/s line‐rate long‐haul DWDM links, including 40×40 Gb/s transmission over KT's standard single‐mode fiber optimized for 10 Gb/s achieves successful results. The proposed upgrading technique allows the Q‐value margin for a 40 Gb/s line rate to be compatible with that of 10 Gb/s.     

60 GHz broadband MAC system design for cable replacement in machine vision applications

In this paper, we present a wireless 60 GHz OFDM transceiver for a high-throughput GigE Vision standard compliant color CCD camera system used in machine vision applications. The OFDM transceiver provides net data rates up to 3.9 Gb/s. The medium access controller (MAC) offers the reliable GigE point-to-point cable replacement functionality with special support of an asymmetrical downlink scenario. The main focus is on the high throughput MAC design for frame based wireless transmissions and the integration onto a hardware platform. The OFDM baseband processor and the MAC were fully implemented in FPGA technology. The performance of the system was theoretically analyzed and measured in an indoor environment. The developed system fulfills the high throughput requirement as well as the low latency requirement of the used industrial HD video camera system.     

20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

Two-dimensional 8×8 photoreceiver array and VCSEL drivers forhigh-throughput optical data links

Two custom GaAs integrated circuits (ICs) have been developed for enabling vertical cavity surface emitting laser (VCSEL) arrays to be used for high throughput spatial division multiplexed (SDM) optical data links. A 16-channel driver IC was developed to drive the VCSEL array and an 8×8 monolithic photoreceiver, which spatially matches the VCSEL array, was developed for receive. Both of these circuits were fabricated in a standard commercial GaAs MESFET process with parasitic photodetectors used for the photoreceivers. Power dissipation and circuit size were primary design challenges for both circuits. The present 8×8 array size along with an estimated usable channel speed of 1 Gb/s allows for an aggregate throughput of 64 Gb/s     

An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-/spl mu/m CMOS

This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver's sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-/spl mu/m digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin.     

High-speed operation of a low-power 4-bit serial-to-parallel converter

This paper presents a high-speed low-power 4-bit superconducting serial-to-parallel converter (SPC) that has been demonstrated experimentally to operate at data rates up to 1 Giga-bits (Gb/s). The primary design goals for this device are high-speed operation, low-power dissipation, and high circuit yield for use as a core element in an address decoder or a demultiplexer. First, the circuit design and optimization are discussed. Simulated performance of the circuit shows proper operation at 20 Gb/s, with a discussion of its potential for use at even higher rates. The power dissipation is computed to be 28 /spl mu/W in continuous operation and the predicted within-wafer yield is 95%. Measured results are then given for data rates of 100 Mb/s and 1 Gb/s.     

一种超小型AES专用处理器的FPGA实现

提出一种基于FPGA的专用处理器设计.它是用于高级加密标准的超小面积设计,支持密钥扩展(现在设计为128位密钥),加密和解密.这个设计采用了完全的8位数据路径宽度,创新的字节替换电路和乘累加器结构,在最小规模的Xilinx Spartan II FPGA芯片XC2S15上实现了一个高级加密标准AES的专用处理器,使用了不到60%的资源.当时钟为70MHz时,可以达到平均加密解密吞吐量2.1Mb/s.主要应用在把低资源占用,低功耗作优先考虑的场合.     

Architectural techniques for eliminating critical feedback paths

The authors demonstrate architectural techniques, for small-state feedback circuits that significantly improve the throughput without requiring circuit design efforts or advanced technologies. The method is flexible in terms of achievable implementations and speedups. The authors discuss a new high-throughput solution for systems with finite-level feedback values. As an example, the authors consider coding and signal processing systems for optical communications, which usually have very simple feedback. The authors demonstrate the method by realizing a 2 micron CMOS layout of a bimode 3B4B line coder. Simulation results show that, using standard cell design, the chip achieves a coding rate of 1.4 Gb/s. Other design options are discussed     

10- and 40-Gb/s forward error correction devices for optical communications

Two standard forward error correction (FEC) devices for 10- and 40-Gb/s optical systems are presented. The first FEC device includes RS(255, 239) FEC, BCH(4359, 4320) FEC, and standard compliant framing and performance monitoring functions. It can support a single 10-Gb/s channel or four asynchronous 2.5-Gb/s channels. The second FEC device implements RS(255, 239) FEC at a data rate of 40 Gb/s. This paper presents the key ideas applied to the design of Reed-Solomon (RS) decoder blocks in these devices, especially those for achieving high throughput and reducing complexity and power. Implemented in a 1.5-V, 0.16-/spl mu/m CMOS technology, the RS decoder in the 10-Gb/s, quad 2.5-Gb/s device has a core gate count of 424 K and consumes 343 mW; the 40-Gb/s RS decoder has a core gate count of 364 K and an estimated power consumption of 360 mW. The 40-Gb/s RS FEC is the highest throughput implementation reported to date.     

Design and performance of an optical path cross-connect systembased on wavelength path concept

This paper describes the system design and performance of an optical path cross-connect (OPXC) system based on wavelength path concept. The (OPXC) is designed to offer 16 sets of input and output fiber ports with each fiber transporting eight multiwavelength signals for optical paths. Each optical path has a capacity of 2.5 Gb/s. Consequently, the total system throughput is 8×16×2.5=320 Gb/s and the OPXC features high modularity and expandability for switch components. By exploiting planar lightwave circuit (PLC) technologies, four sets of (8×16) delivery-and-coupling-type optical switches (DC-switches) are developed for the 320 Gb/s throughput OPXC system. The DC-switch offers the average insertion-loss of 12.6 dB and ON/OFF ratio of 42.1 dB. The PLC arrayed-waveguide gratings are confirmed to successfully demultiplex the eight directly modulated signals, multiplexed at a spacing of 1 nm, with a crosstalk of under -25 dB. Eight wavelength-division multiplexing signals, directly modulated at 2.5 Gb/s, are confirmed to be transported over 330 km via a cross-connection node in the test-bed system that simulates five-node network. The experimental performances demonstrated In this paper ensures full scale implementation of the proposed optical path cross-connect system with 320 Gb/s throughput and high integrity     

A 640-Mb/s 2048-bit programmable LDPC decoder chip

A 14.3-mm/sup 2/ code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-/spl mu/m six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.     

一种用于14位250 MS/s ADC的3.5 Gb/s发送器

提出了一种用于14位250 MS/s ADC的数据发送器。该发送器输出采用电流模驱动方式,最高数据传输速率达3.5 Gb/s,数据输出仅需要2个数据端口。电路采用180 nm 1.8 V 1P5M CMOS工艺实现。测试结果表明,该发送器在3.5 Gb/s速率下的输出信号摆幅为800 mV,抖动峰峰值为100 ps,功耗为32 mW。采用该3.5 Gb/s数据发送器的ADC在250 MHz采样率下得到的信噪比为71.1 dBFS,无杂散动态范围为77.6 dB。     

A new methodology to implement the AES algorithm using partial and dynamic reconfiguration

Wireless networks are very widespread nowadays, so secure and fast cryptographic algorithms are needed. The most widely used security technology in wireless computer networks is WPA2, which employs the AES algorithm, a powerful and robust cryptographic algorithm. In order not to degrade the Quality of Service (QoS) of these networks, the encryption speed is very important, for which reason we have implemented the AES algorithm in an FPGA, taking advantage of the hardware characteristics and the software-like flexibility of these devices. In this paper, we propose our own methodology for doing an FPGA-based AES implementation. This methodology combines the use of three hardware languages (Handel-C, VHDL and JBits) with partial and dynamic reconfiguration, and a pipelined and parallel implementation. The same design methodology could be extended to other cryptographic algorithms. Thanks to all these improvements our pipelined and parallel implementation reaches a very high throughput (24.922 Gb/s) and the best efficiency (throughput/area ratio) of all the related works found in the literature (6.97 Mb/s per slice).