基于扫描森林结构的种子编码方案

扫描森林是一种有效的扫描结构，它能够大幅度地降低测试应用开销、测试功耗以及测试数据容量。该文针对采用扫描森林结构的待测电路提出了一种新的种子编码方案。在该方案中，伪随机测试向量覆盖电路中的易测故障，使用ATPG对剩余故障生成确定性测试向量，将其中某一测试向量对应的种子编码为LFSR扩展成该向量需要运行的时钟周期数。实验结果表明，提出的方案能大幅度地降低种子存储数据量，最大降幅达到了83.3％。     

提高瞬态电流自动测试生成时间效率的方法

瞬态电流测试可以检测一些用电压测试和稳态电流测试不能检测的故障。对每一个故障都进行一次测试生成所花费的时间太多,而且没有必要。针对用瞬态电流测试来检测晶体管开路故障（Stuckopen Fault）,研究精简故障数目,提高测试生成效率的方法。通过从靠近电路原始输出端向原始输入端逐渐进行测试生成以及其他一些办法,可以明显提高测试生成的时间效率。模拟实验结果表明,测试生成算法执行时间大约减少了70%。     

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test channel requirements. To address these problems, researchers have proposed numerous test compression architectures. In this article, we propose a flexible scan test methodology called universal multicasting scan (UMC scan). It has three major features: First, it provides a better than state-of-the-art test compression ratio using multicasting. Second, it accepts any existing test patterns and doesn't need ATPG support. Third, unlike most previous multicasting schemes that use mapping logic to partition the scan chains into hard configurations, UMC scan's compatible scan chain groups are defined by control bits, as in the segmented addressable scan (SAS) architecture. We have developed several techniques to reduce the extra control bits so that the overall test compression ratio can approach that of the ideal multicasting scheme.     

基于SAT的多目标故障测试向量动态压缩方法

针对传统的自动测试图形向量生成采用逐个求解单一故障模型导致生成测试向量数据量巨大的缺点, 提出一种基于布尔满足性(boolean satisfiability, SAT)的多目标故障测试向量动态压缩方法, 同时论证多目标故障测试生成问题为布尔满足性问题。该方法将具有鲁棒性的SAT算法嵌入经典的动态压缩流程中, 首先利用经典动态压缩算法求解最小测试向量检测大部分失效故障, 然后采用SAT求解器对未测出的多故障电路进行同一求解和附加约束求解方式, 最终得到故障覆盖率高的测试向量和同一测试最大故障列表。实验数据表明, 在相同电路模型情况下, 此方法求得的测试向量相比经典动态压缩减少高达70%。     

低成本的两级扫描测试结构

提出了一种两级扫描测试结构：根据电路结构信息对时序单元进行分组,同组的时序单元在测试生成电路中共享同一个伪输入;将时序单元划分到不同的时钟域,在测试向量的置入过程中只有很小一部分时序单元发生逻辑值的翻转;引入新的异或网络结构,消除了故障屏蔽效应.实验结果表明,该两级测试结构与以往的方法相比,在保证故障覆盖率的同时,大大降低了测试时间、测试功耗和测试数据量.     

Dynamic scan: driving down the cost of test

Two factors primarily drive the soaring cost of semiconductor test: the number of test patterns applied to each chip and the time it takes to run each pattern. Typical semiconductor testing for each chip involves a set of 1,000 to 5,000 test patterns. These tests are applied through scan chains that operate at about 25 MHz. Depending on the size of the scan chains on the chip, a set of test patterns can take a few seconds to execute per chip. It's easy to see that even a small decrease in either the number of patterns or the time to execute them can quickly add up to big savings across millions of fabricated chips. This potential savings forms the basis for dynamic scan, a new approach to the well-established scan test methodology. The authors initial studies indicate that dynamic scan could easily reduce the time spent applying test patterns by 40 percent. A more theoretical analysis shows a potential savings of as much as 80 percent.     

一个适于形式验证的ATPG引擎

自动测试产生(ATPG)不仅应用于芯片测试向量生成，也是芯片设计验证的重要引擎之一．提出了一种组合电路测试产生的代数方法，既可作为组合验证的ATPG引擎，又可用于通常的测试产生．该算法充分发挥了二叉判决图(BDD)及布尔可满足性(SAT)的优势，通过启发式策略实现SAT算法与BDD算法的交替，防止因构造BDD可能导致的内存爆炸，而且使用增量的可满足性算法，进一步提高了算法的效率．实验结果表明了该算法的可行性和有效性．     

用扫描链重构来提高EFDR编码的测试压缩率和降低测试功耗

为了解决系统芯片测试中日益增长的测试数据和测试功耗的问题,提出一种不影响芯片正常逻辑功能的扫描链重构算法--Run-Reduced-Reconfiguration(3R).该算法针对扩展频率导向游程(EFDR)编码来重排序扫描链和调整扫描单元极性,重新组织测试数据,减少了游程的数量.从而大人提高了EFDR编码的测试压缩率并降低测试功耗;分析了扫描链调整对布线长度带来的影响后,给出了权衡压缩率和布线长度的解决方案.在ISCAS89基准电路上的实验结果表明,使用3R算法后,测试压缩率提高了52%,测试移位功耗降低了53%.     

Developing a high-level fault simulation standard

Recent developments in deep-submicron technology challenge current integrated circuit testing methods. The increasing complexity of designed systems makes test development more time-consuming. Moreover, nanometer technology introduces new defects or higher data rate errors. To reduce manufacturing costs and time to market, we must develop efficient fault detection and location methods. Using high-level fault simulation stimulates the development of new, fast test-generation algorithms that take into consideration functional features of the system under test or its components. Moreover, all synthesis tools migrate to higher levels, and we believe that this will improve ATPG tools as well     

ASIC集成电路的可测性设计与技术实现

ASIC集成电路设计开发中的隐含逻辑瑕疵与电路故障是芯片实现的最大困境,针对不同特性的电路提出了内部逻辑扫描、存储器内建自测试、边界扫描链插入以及ATPG自动测试向量生成的解决方案与技术方法,实现了SOC设计开发中逻辑与成片电路的主动侦测与跟踪寻径,经实践证明这些方法大大提高了复杂SOC研制的成功率.     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

This paper describes the design-for-testability(DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test(BIST) circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops(PLL) to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design,the test strategies for this case are quite complex,with complicated automatic test pattern generation(ATPG) and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing(HVM) DFT plan to meet high quality test goals as well as slow test power consumption and cost.     

Fast and energy-frugal deterministic test through efficient compression and compaction techniques

Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the scan chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also scan chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology.     

含存储器数字电路系统的自动测试生成

已有的数字电路自动测试生成(ATPG)软件没有存储器的结构模型，不支持对存储器电路的自动测试生成。该文分析了2类存储器的功能特征，提出了面向测试的ROM和RAM结构模型的建立方法，其中，ROM根据所储存的数据等效成组合电路模型， RAM利用新建立的RAMBIT基元等效成利于测试的时序电路模型。将其应用于ATPG软件中，解决了含存储器数字电路的自动测试生成问题。     

减少多种子内建自测试方法硬件开销的有效途径

提出一个基于重复播种的新颖的BIST方案，该方案使用侦测随机向量难测故障的测试向量作为种子，并利用种子产生过程中剩余的随意位进行存储压缩；通过最小化种子的测试序列以减少测试施加时间．实验表明，该方案需要外加硬件少，测试施加时间较短，故障覆盖率高，近似等于所依赖的ATPG工具的故障覆盖率．在扼要回顾常见的确定性BIST方案的基础上，着重介绍了文中的压缩存储硬件的方法、合成方法和实验结果．     

逻辑内建自测试高故障覆盖率设计

基于扫描的可测性设计技术需要大量空间存储测试矢量,并且难以实现全速测试,随着芯片规模越来越大,频率越来越高,其测试成本也将越来越高,逻辑内建自测试(Logic Built-In-Self-Test,LBIST)技术以其简单的硬件实现和较小的设计开销开始被业界广泛使用,但该技术也存在覆盖率较低的问题,主要原因在于:一是线性反馈移位寄存器(Linear Feedback Shift Register,LFSR)产生的伪随机矢量的空间相关性;二是电路结构上对伪随机矢量的抵抗性;针对这两种原因给出了一些改善的方法,从而达到提高故障覆盖率的目的,为实际设计提供借鉴。     

针对扫描阻塞结构的测试数据压缩方案*

分析了集成电路测试面临的测试数据量大、测试应用时间长等问题,对常用的测试压缩方法进行了介绍,并在扫描阻塞测试结构基础上,提出了对数据进行部分编码压缩的方案。在附加硬件开销很小的情况下,进一步压缩了测试数据。理论分析和实验结果都表明了本压缩方案的可行性和有效性。     

基于STM32的100 L/min尘埃粒子计数器控制系统设计

针对传统尘埃粒子计数器检测规格小、精度差、体积大、功能单一等问题,设计了一种新型的尘埃粒子计数器控制系统.控制系统以STM32F103芯片为核心,通过信号分级采样电路、放大电路、电源电路和通信电路实现对流量和粒子信号的采集与处理,并将结果通过触摸屏显示.运行结果表明:本控制系统运行过程稳定,检测规格可达100 L/min,可检测6路不同规格的粒子数,最小能够检测0.3 μm的尘埃粒子,并且检测结果满足国家计量检测标准.     

Enhancing encoding capacity of combinational test stimulus decompressors

While scan-based compression is widely utilized in order to alleviate the test time and data volume problems,the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable patterns.Aggressively increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns,degrading the overall compression level.In this paper,we present various methods to improve the ratio of encodable patterns.These methods are b...     

一种6读2写多端口寄存器堆的全定制实现

采用全定制设计方法实现了一种6读2写的3232位的多端口寄存器堆，包括结构设计、电路设计、版图设计、仿真验证以及建模建库。该多端口寄存器堆的读写端口互相独立，在一个时钟周期内，能够同时读出6个32位数据，并写入2个32位数据。在电路实现上，采用高速SCL结构的地址译码和分组字线的方法来减少读写延迟。采用了0.18µm 6层金属P阱CMOS工艺来实现版图设计，通过了版图验证和后端仿真。