Simulating the current mirror with a self-heating BJT model

A Gummel-Poon (GP) BJT (bipolar junction transistor) model that includes self-heating is presented, and a current-mirror circuit is used to show its significance. Self-heating thermal effects are modeled by a simple electrical analog circuit, which also provides BJT junction temperature as part of the CAD solution. Both discrete-BJT and IC mirror circuits are tested. The self-heating model correctly simulates the temperature stability of the IC mirror circuit where the BJTs are in close thermal proximity. For the discrete-BJT circuit, a standard GP model produces errors up to 84% versus 6.1% for the self-heating model     

Scalable small-signal model for BJT self-heating

The effects of self-heating on BJT (bipolar junction transistor) behavior are demonstrated through measurement and simulation. Most affected are the small-signal parameters Y₂₂ and Y₁₂. A frequency-domain solution to the heat-flow equation is presented. It applies to any rectangular emitter geometry. This model, although simple enough for CAD, predicts thermal spreading impedance with good accuracy for a wide range of frequencies     

Impact of self-heating and thermal coupling on analog circuits inSOI CMOS

This paper examines the influence of the static and dynamic electrothermal behavior of silicon-on-insulator (SOI) CMOS transistors on a range of primitive analog circuit cells. In addition to the more well-known self-heating close-range thermal coupling effects are also examined. Particular emphasis is given to the impact of these effects on drain current mismatch due to localized temperature differences. Dynamic electrothermal behavior in the time and frequency domains is also considered, measurements and analyses are presented for a simple amplifier stage, current mirrors, a current output D/A converter, and ring oscillators fabricated in a 0.7-μm SOI CMOS process. It is shown that circuits which rely strongly on matching, such as the current mirrors or D/A converter, are significantly affected by self-heating and thermal coupling. Anomalies due to self-heating are also clearly visible in the small-signal characteristics of the amplifier stage. Self-heating effects are less significant for fast switching circuits. The paper demonstrates how circuit-level simulations can be used to predict undesirable nonisothermal operating conditions during the design stage     

Analysis of the large-signal characteristics of powerheterojunction bipolar transistors exhibiting self-heating effects

The large-signal microwave characteristics of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) are modeled using the conventional Gummel-Poon-based bipolar junction transistor (BJT) model and extending it to include self-heating effects. The model is incorporated as a user-defined model in a commercial circuit simulator. The experimental microwave characteristics of HBTs are analyzed using the new model and harmonic balance techniques and the impact of self-heating effects on the device large-signal characteristics is investigated. Use of constant base voltage rather than constant current is more suitable for achieving maximum output power. Self-heating induced by RF drive is reduced under constant base current conditions. Increased thermal capacitance values result in gain enhancement at high power levels     

模电教学中BJT与MOS的近似性分析

BJT 与MOS器件及电路是模电重要内容；教学中二者的电路模型与分析方法不一致，学生困惑于两套不同的器件及电路知识。本文在遵循器件及电路工作原理的基础上，首次将二者在小信号模型、电路参数、I-V方程、特性曲线、工作区间、指标计算上进行完整的近似性分析及一致性推导；在二者电路计算中，用三种单管单级放大器实例，阐述近似分析方法的便利性。本文是模电教学的有力补充。     

A unified model for single/multifinger HBTs including self-heatingeffects

This paper presents a unified analytical large-signal model that includes self-heating effects. The model is applied to a single-finger AlGaAs/GaAs heterojunction bipolar transistor (HBT) and a multifinger InGaAs/GaAs HBT. The self-heating effect in the HBT is simulated as a feedback from the collector current to the base-emitter voltage. The main advantage of the circuit presented here is that additional analysis of coupling between electrical and thermal circuits is not required, as is the case with the existing models. The small-signal HBT model is implemented based on the S-parameters at multiple frequencies measured at multiple bias points. This model is verified by comparing the measured and simulated S-parameters. The large-signal model is based on the forward Gummel plot and is built over the small-signal model. This model is verified by comparing the simulated and measured dc I-V characteristics     

Thermal analysis of AlGaN-GaN power HFETs

In this paper, we present a thermal analysis of AlGaN-GaN power heterojunction field-effect transistors (HFETs). We report the dc, small-signal, large-signal, and noise performances of AlGaN-GaN HFETs at high temperatures. The temperature coefficients measured for GaN HFETs are lower than that of GaAs pseudomorphic high electron-mobility transistors, confirming the potential of GaN for high-temperature applications. In addition, the impact of thermal effects on the device dc, small-signal, and large-signal characteristics is quantified using a set of pulsed and continuous wave measurement setups. Finally, a thermal model of a GaN field-effect transistor is implemented to determine design rules to optimize the heat flow and overcome self-heating. Arguments from a device, circuit, and packaging perspective are presented.     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

Fully coupled electrothermal mixed-mode device simulation of SiGeHBT circuits

It is well known that for the design and simulation of state-of-the-art circuits thermal effects like self-heating and coupling between individual devices must be taken into account. As compact models for modern or experimental devices are not readily available, a mixed-mode device simulator capable of thermal simulation is a valuable source of information, Considering self-heating and coupling effects results in a very complex equation system which can only be solved using sophisticated techniques. We present a fully coupled electrothermal mixed-mode simulation of an SiGe HBT circuit using the design of the μA709 operational amplifier. By investigating the influence of self-heating effects on the device behavior we demonstrate that the consideration of a simple power dissipation model instead of the lattice heat flow equation is a very good approximation of the more computation time consuming solution of the lattice heat flow equation     

Simulation and modeling-a CAD model for the BJT with self heating

A Gummel-Poon model that accounts for self heating in the bipolar-junction (BJT) transistor is presented. The model uses a simple but flexible RC analog circuit for thermal effects. Junction temperature as a voltage is a byproduct of the modeling approach. In contrast to the standard model, this model does not require changes in BJT parameters in order to track circuit changes that affect BJT dissipated power. Although not presented here, transient behavior due to self heating and thermal capacitance has been tested, and it is also correctly predicted by this model     

Monolithic bipolar diodes and their models

The AC performance of the diode-connected, bipolar junction transistor (BJT) is examined. The discussion covers the BJT's most common connection, its small-signal behavior, and the current repeater that uses the diode as an input device. Looking at the AC behavior reveals the strengths and weaknesses of various models and simulators, primarily SPICE. It is shown that these common circuits are classic cases where models can fail     

SOI thermal impedance extraction methodology and its significancefor circuit simulation

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R_th) and thermal capacitance (C_th) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits     

Analysis of ATPMOS configurations-based 4 × 1 multiplexer with estimation of power and delay

In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor (ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS and DT ATPMOS) are implemented on a 4 × 1 (multiplexer) mux circuit. Leakage power dissipation, dynamic power dissipation and delay performance parameters are calculated for both (ST ATPMOS and DT ATPMOS) ATPMOS configurations-based 4 × 1 mux circuits at different values of transistor’s width. Due to simulation, it is realised that the leakage power dissipation and dynamic power dissipation are reduced and delay is improved (delay is reduced) in the DT ATPMOS configuration-based mux circuit compared to the ST ATPMOS configuration-based mux circuit. The whole simulation process was carried out in 45-nm technology. The circuits were operated at 1-V power supply.     

用于射频标签的低功耗上电复位电路

介绍了一种用于射频标签芯片中数字逻辑部分的上电复位电路。该上电复位电路适应于低电源电压的芯片,改变MOS晶体管的参数以及延迟时间可以调节脉冲的宽度和数字门电路加宽脉冲的宽度,通过反馈管,电路能够抵抗比较大的电源电压噪声影响。电路产生上电复位信号脉冲后,通过反馈控制使能端信号关断整个电路,实现低功耗。电路采用华虹NEC公司0.13μm标准CMOS工艺流片,测试结果表明,此电路能够输出有效的脉冲信号;脉冲过后的导通电流基本为0。FPGA平台的验证表明,芯片输出的POR信号能够正确启动标签中的数字基带芯片,输出信号有效。     

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective

Ultralow-power dissipation can be achieved by operating digital circuits with scaled supply voltages, albeit with degradation in speed and increased susceptibility to parameter variations. However, operating digital logic and memory circuits in the subthreshold region (supply voltage less than the transistor threshold voltage) for ultralow-power operations requires device, circuit as well as architectural design optimizations, different from the conventional superthreshold design. This paper analyzes such optimizations from energy dissipation point of view and shows that it is feasible to achieve robust operation of ultralow-voltage systems. Operation with power supply as low as 60 mV is demonstrated. Techniques to reduce the impact of process variations on subthreshold circuits are also discussed. In addition, it is shown that subthreshold leakage current can be useful for other applications like thermal sensors.      

有射极电阻的基本电路中双极型晶体三极管工作状态的一种判断方法

本文给出含有射极电阻的基本电路中双极型晶体三极管(BJT)工作状态的一种判断方法。对于有射极电阻的基本电路,如果只知道电路中电阻的阻值、BJT的电流放大倍数β和直流电源的电压值,可以先假设其中的BJT处于放大状态,求出BJT在放大状态下的集电极电流IC或基极电流IB,然后与临界饱和状态下的集电极电流ICS或基极电流IBS比较,如果IC相似文献   

晶体管混合π型参数与Y参数的关系

晶体管高频小信号等效电路模型可用两种方法得到:一是把晶体管视为一个二端口网络,列出电流、电压方程式,拟定满足方程的网络模型,常采用Y参数模型;二是根据晶体管内部发生的物理过程来拟定的模型,即π型参数模型;同一个晶体管应用在不同场合可用不同的等效电路表示,同一晶体管的各种等效电路之间又应该是互相等效的,各等效电路中的参数可互相转换。     

Transistor equivalent circuits

This paper surveys the history of the electric-circuit representation of the transistor over the past fifty years. During the first two decades after the transistor was announced in 1948, primary emphasis was on small-signal equivalent circuits, which could be used for linear-circuit analysis and design. In addition, parameters of many of these equivalent circuits for the bipolar junction transistor, which are described, were related to the physical construction of the device. Approximately two-thirds of the paper is devoted to this period, when the writer personally contributed to this effort. By the beginning of the third decade, transistor circuits had became more complex, and circuit analysis was carried out with the help of digital computers. Interest then shifted away from small-signal equivalent circuits to “models” for computer-aided circuit design (CACD). This transition, including the models used in the widely used CACD program SPICE, is described. MOS transistors are treated only briefly; by the time MOS transistors became commercially viable devices, emphasis then also had shifted to “models” for CACD. In conclusion, the writer notes that there is still hope for us aficionados of small-signal equivalent circuits; new types of transistors are still being characterized in this manner     

Electrothermal analysis of GaN power submicron field-effect heterotransistors

Physical processes and self-heating factors of in a power submicron field-effect heterotransistor have been considered. Mathematical models were proposed and the electrothermal analysis of heterotransistor parameters and characteristics was performed. The impact of thermal processes on parameters of the circuit model and the output frequency characteristics of submicron heterotransistor was shown on the basis of analysis of temperature fields. The relationship of the transistor thermal resistance as a function of its geometry and thermophysical parameters has been established.     

Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies