共查询到20条相似文献,搜索用时 15 毫秒
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Massimo Conti Paolo Crippa Simone Orcioni Claudio Turchetti 《Analog Integrated Circuits and Signal Processing》2001,29(3):181-199
In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method. 相似文献
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Pfingsten T. Herrmann D. J. L. Rasmussen C. E. 《Semiconductor Manufacturing, IEEE Transactions on》2006,19(4):475-486
Fluctuations are inherent to any fabrication process. Integrated circuits and microelectromechanical systems are particularly affected by these variations, and due to high-quality requirements the effect on the devices' performance has to be understood quantitatively. In recent years, it has become possible to model the performance of such complex systems on the basis of design specifications, and model-based sensitivity analysis has made its way into industrial engineering. We show how an efficient Bayesian approach, using a Gaussian process prior, can replace the commonly used brute-force Monte Carlo scheme, making it possible to apply the analysis to computationally costly models. We introduce a number of global, statistically justified sensitivity measures for design analysis and optimization. Two models of integrated systems serve us as case studies to introduce the analysis and to assess its convergence properties. We show that the Bayesian Monte Carlo scheme can save costly simulation runs and can ensure a reliable accuracy of the analysis 相似文献
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Saxena S. Hess C. Karbasi H. Rossoni A. Tonello S. McNamara P. Lucherini S. Minehane S. Dolainsky C. Quarantelli M. 《Electron Devices, IEEE Transactions on》2008,55(1):131-144
Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described. 相似文献
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《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(8):692-696
Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies. 相似文献
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适用于有线网络时传统独立分层协议阻碍和限制了未来IMT—Advanced无线网络性能进一步提升,无线网络的发展需要新的优化技术与之相适应。高效跨层、跨模块的资源优化技术,通过发掘各层次、各模块之间的冗余信息,或压缩,或利用,能够明显地改善无线系统性能。跨层优化技术在结合认知科学技术、人工智能技术、凸优化等数学手段的基础上,能对各模块资源合理优化分配,最大程度地提高无线系统的资源利用效率,为网络内无线节点提供更好的业务服务质量(QoS)保障以及用户体验。 相似文献
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Lee D. Blaauw D. Sylvester D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(10):1075-1088
Runtime leakage current, defined as circuit leakage during normal operation (i.e., nonstandby mode), has become a major concern in very advanced technologies along with traditional standby mode leakage. In this paper, we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, meaning that they have either high or low values. We then propose a method that exploits these skewed state probabilities by setting only those transistors to high-Vt (thick-oxide) that have a high likelihood of being off (on) and, hence, contributing significantly to the total runtime leakage. Accordingly, we also propose a library specifically tailored to the proposed approach, where Vt and Tox assignment with favorable tradeoffs under skewed input probabilities is provided. For further leakage reduction, we also introduce circuit resynthesis using pin reordering, pin rewiring, mapping, and decomposition. The optimization algorithm shows substantial leakage improvement over probability unaware optimization using a traditional standard cell library 相似文献
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In practical reliability optimization models, finding an optimal solution to the model is not the only requirement. One may also be interested in solutions that are close to optimum, or one may want to know what happens if a change is made in the model. This paper presents new reliability optimization models which can be formulated as parametric nonlinear integer programming problems. Solution methods are illustrated with examples and flow charts. 相似文献
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采用建立管芯等效电路模型、灵敏度分析以及统计勘探法对微波单片集成电路进行成品率优化,并编制了软件,加入到GaAsICCAD系统中。应用该软件对X波段低噪声MMIC、超宽带MMIC放大器进行了设计,成品率有较大的提高,电路性能有所改善。 相似文献
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SRAM的泄漏功耗是超大规模集成电路设计中需要满足的一个重要指标,对SRAM泄漏功耗的估算也是设计中需要解决的一个重要问题.通过分析SRAM的结构组成,建立各组成部分在不同工作状态下的泄漏功耗模型,利用建立模型进行功耗估算.仿真结果表明,建立的模型能够对不同尺寸的SRAM的泄漏功耗进行快速的估算,而且误差可以接受. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(12):1749-1752
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《Semiconductor Manufacturing, IEEE Transactions on》2008,21(2):244-247
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《Microwave Theory and Techniques》1965,13(2):162-167
The effect of a different value of series resistance associated with the varactor in its imbedding at each of the important frequencies present in a one-port parametric amplifier is analyzed. The modified equations for effective noise temperature, amplifier gain and pump power required thus obtained are compared to experimental values measured on a 4.8 Gc/s parametric amplifier. Finally a simple and precise method for adjusting the amplifier to get close correlation between the measured varactor parameters using Kurokawa's method at signal idler, and pump frequencies and the overall amplifier performance is presented. 相似文献
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