Parametric Yield Optimization of MOS IC's Affected by Device Mismatch

In this paper a statistical design procedure for the parametric yield optimization based on Simulated Annealing and Quasi-Newton algorithms is presented. A rigorous formulation of the yield taking into account both inter-die and intra-die (mismatch) device variations has been used in defining the procedure steps. A reduction in the complexity of the yield optimization algorithm is achieved by performing a screening of the parameters, discarding those having small effect on the required performance. Application examples evidence the achievement of the method.     

Model-Based Design Analysis and Yield Optimization

Fluctuations are inherent to any fabrication process. Integrated circuits and microelectromechanical systems are particularly affected by these variations, and due to high-quality requirements the effect on the devices' performance has to be understood quantitatively. In recent years, it has become possible to model the performance of such complex systems on the basis of design specifications, and model-based sensitivity analysis has made its way into industrial engineering. We show how an efficient Bayesian approach, using a Gaussian process prior, can replace the commonly used brute-force Monte Carlo scheme, making it possible to apply the analysis to computationally costly models. We introduce a number of global, statistically justified sensitivity measures for design analysis and optimization. Two models of integrated systems serve us as case studies to introduce the analysis and to assess its convergence properties. We show that the Bayesian Monte Carlo scheme can save costly simulation runs and can ensure a reliable accuracy of the analysis     

VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.     

Variation in Transistor Performance and Leakage in Nanometer-Scale Technologies

Variation in transistor characteristics is increasing as CMOS transistors are scaled to nanometer feature sizes. This increase in transistor variability poses a serious challenge to the cost-effective utilization of scaled technologies. Meeting this challenge requires comprehensive and efficient approaches for variability characterization, minimization, and mitigation. This paper describes an efficient infrastructure for characterizing the various types of variation in transistor characteristics. A sample of results obtained from applying this infrastructure to a number of technologies at the 90-, 65-, and 45-nm nodes is presented. This paper then illustrates the impact of the observed variability on SRAM, analog and digital circuit blocks used in system-on-chip designs. Different approaches for minimizing transistor variation and mitigating its impact on product performance and yield are also described.     

IC参数成品率全局优化的映射距离最小化算法

提出了一种新的集成电路参数成品率的全局优化算法--映射距离最小化算法.该算法采用了均匀设计与映射距离最小的耦合优化,每次迭代模拟次数很少,优化过程明显加速.另外,给出了一种粗略估计空间点集均匀性的方法--k近邻密度估计,在有效时间内判断一个空间点集的均匀性.模拟结果表明,该算法对集成电路进行快速成品率优化设计及提高电路设计的稳定性具有较好的应用价值.     

IC参数成品率全局优化的映射距离最小化算法

提出了一种新的集成电路参数成品率的全局优化算法--映射距离最小化算法.该算法采用了均匀设计与映射距离最小的耦合优化,每次迭代模拟次数很少,优化过程明显加速.另外,给出了一种粗略估计空间点集均匀性的方法--k近邻密度估计,在有效时间内判断一个空间点集的均匀性.模拟结果表明,该算法对集成电路进行快速成品率优化设计及提高电路设计的稳定性具有较好的应用价值.     

VLSI成品率预测与仿真

本文建立ＩＣ光刻工艺相关缺陷计算模型和基于Ｍｏｎｔｅ Ｃａｒｌｏ统计成品率计算模型。阐述了集成电路功能优品率仿真系统ＸＤ－ＹＥＳ实现，讨论了应用ＸＤ－ＹＥＳ实现的功能成品率设计，并给出该系统实用性验证。研究分析表明，其结果与实际结果符合很好。     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

IMT—Advanced跨层优化技术

适用于有线网络时传统独立分层协议阻碍和限制了未来IMT—Advanced无线网络性能进一步提升,无线网络的发展需要新的优化技术与之相适应。高效跨层、跨模块的资源优化技术,通过发掘各层次、各模块之间的冗余信息,或压缩,或利用,能够明显地改善无线系统性能。跨层优化技术在结合认知科学技术、人工智能技术、凸优化等数学手段的基础上,能对各模块资源合理优化分配,最大程度地提高无线系统的资源利用效率,为网络内无线节点提供更好的业务服务质量（QoS）保障以及用户体验。     

Runtime Leakage Minimization Through Probability-Aware Optimization

Runtime leakage current, defined as circuit leakage during normal operation (i.e., nonstandby mode), has become a major concern in very advanced technologies along with traditional standby mode leakage. In this paper, we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, meaning that they have either high or low values. We then propose a method that exploits these skewed state probabilities by setting only those transistors to high-V_t (thick-oxide) that have a high likelihood of being off (on) and, hence, contributing significantly to the total runtime leakage. Accordingly, we also propose a library specifically tailored to the proposed approach, where V_t and T_ox assignment with favorable tradeoffs under skewed input probabilities is provided. For further leakage reduction, we also introduce circuit resynthesis using pin reordering, pin rewiring, mapping, and decomposition. The optimization algorithm shows substantial leakage improvement over probability unaware optimization using a traditional standard cell library     

IPv6的移动性支持及其优化

随着IPv6技术的稳步发展以及移动IPv4面临移动性、安全性差等越来越多的问题，移动IPv6由于其优良的性能而日益引起人们的关注。由于目前并未出现移动IPv6的标准，本文根据IETF关于IPv6的移动性支持的草案，首先详细介绍了移动IPv6的基本概念和工作原理，主要包括3个基本功能：路由器搜索、注册和分组传送。然后，文章对移动IPv6的优化问题进行了初步探讨。最后简单分析了移动IPv6技术未来的发展和实现。     

Parametric Programming Applied to Reliability Optimization Problems

In practical reliability optimization models, finding an optimal solution to the model is not the only requirement. One may also be interested in solutions that are close to optimum, or one may want to know what happens if a change is made in the model. This paper presents new reliability optimization models which can be formulated as parametric nonlinear integer programming problems. Solution methods are illustrated with examples and flow charts.     

微波单片集成电路的成品率优化

采用建立管芯等效电路模型、灵敏度分析以及统计勘探法对微波单片集成电路进行成品率优化，并编制了软件，加入到ＧａＡｓＩＣＣＡＤ系统中。应用该软件对Ｘ波段低噪声ＭＭＩＣ、超宽带ＭＭＩＣ放大器进行了设计，成品率有较大的提高，电路性能有所改善。     

一种新型的参量阵扬声器阵列设计与优化

超声传感器阵列指向性决定了参量阵扬声器再现音频指向性的性能.提高超声发射阵的指向性也是实现高指向性低频声波的关键技术之一.基于阵列指向性基本理论及与线列阵组合平面阵进行分析比较,提出了一种球面六边形阵列.仿真试验结果表明,球面六边形阵列扬声器不仅完全消除栅瓣,主瓣宽度也更窄.且采用改进的遗传算法通过幅度加权优化该阵列使其旁瓣级低于-20 dB,进一步优化了指向性性能.     

SRAM泄漏功耗分析和估算

SRAM的泄漏功耗是超大规模集成电路设计中需要满足的一个重要指标,对SRAM泄漏功耗的估算也是设计中需要解决的一个重要问题.通过分析SRAM的结构组成,建立各组成部分在不同工作状态下的泄漏功耗模型,利用建立模型进行功耗估算.仿真结果表明,建立的模型能够对不同尺寸的SRAM的泄漏功耗进行快速的估算,而且误差可以接受.     

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies

To minimize the leakage power dissipation of present-day on-chip Decaps, we propose a gated decoupling capacitor (GDecap) technique that deactivates a Decap when it is not needed. The application of the proposed GDecap technique on an eight-way clock-gated clustered pipeline showed that on average, 41.7% Decap leakage power was reduced, with negligible $ ({sim 0.037}%)$ worst-case performance degradation, at the 70-nm technology node. GDecap design incurred an area overhead of around 5.36% when compared with a conventional Decap design.      

New Test Structure to Monitor Contact-to-Poly Leakage in Sub-90 nm CMOS Technologies

The high leakage or even direct short between contact and gate is a serious problem after the feature sizes are shrunk to 65-nm technology and beyond. However, there is no suitable test structure to effectively monitor the leakage current between them. We have designed a new test structure which can eliminate the drawbacks of existing test structures and effectively monitor the leakage current between contact and gate electrode in state-of-the-art CMOS process technology.      

Parametric Amplifier Noise Analysis

The effect of a different value of series resistance associated with the varactor in its imbedding at each of the important frequencies present in a one-port parametric amplifier is analyzed. The modified equations for effective noise temperature, amplifier gain and pump power required thus obtained are compared to experimental values measured on a 4.8 Gc/s parametric amplifier. Finally a simple and precise method for adjusting the amplifier to get close correlation between the measured varactor parameters using Kurokawa's method at signal idler, and pump frequencies and the overall amplifier performance is presented.     

城域传输网的规划与优化方法

传输网是电信业务的承载网,是保证整个网络质量的关键.本文根据目前城域传输网存在的资源配置不合理的问题,分别针对光缆网、设备网讨论了相应的优化和规划方法.注重通过科学评估网络,利用网络优化来提高网络资源利用率,最后结合具体例子进行了说明.     

A Multiobjective Parametric Optimization for Passenger-Car Steering Actuator

A robust design for the size optimization of a motor-driven steer applied in a compact car, using the design of simulation trial, is described and illustrated in this paper. The objective of the optimal design using the combined design of simulation trial and finite-element analysis (FEA) approach is to ensure that the motor-driven steer's performance for compact cars is insensitive to noise, with moderate computational effort. The optimal design process takes into consideration noises that arise in the unexpected load condition, such as tolerances for parameter variation of the electric motor and reduction gear in the actuator. The optimization is realized by a simulation and analysis tool that integrates the Target-wise Parameter Optimization and the FEA. The proposed procedure can not only reduce the size of an actuator but also raise the system efficiency of the motor-driven steering (MDS). In this paper, we have used an orthogonal array ${rm L}18(2^{1} times 3^{7})$ to implement simulation trials and made a response table and graph of control factors. Eventually, the optimal values of the control factors, the diameter of the stator core, the width of the wire, the turn number of the wire, the gear ratio of the worm and worm-wheel gear, the surface flux density of the magnet, the armature core's stack factor, and the module ratio of the worm and worm-wheel gear were decided, and then, the signal-to-noise ratio (SNR) was increased to 20.58%. The simulation results demonstrated that the proposed method applied to the optimal design of the MDS' actuator was feasible and efficient. In this paper, the design optimization process is described, and the results are presented.