Characteristics of 4H-SiC Pt-gate metal-semiconductor field-effect transistor for use at high temperatures

The 4H-SiC Pt recessed gate metal-semiconductor field-effect transistor (MESFET) was fabricated by reactive ion etching (RIE) for device isolation. The device exhibited a pinch-off voltage of − 9 V, transconductance (g_m) of 19.2 mS/mm, and gate breakdown voltage of − 115 V at room temperature. The characteristics of this MESFET were investigated at high temperatures. It was shown that the MESFET can operate at 560 °C. The time dependence of the I_DS of a MESFET was also investigated at 400 °C in an Ar atmosphere. The change of I_DS (V_G = 0 V) was less than 5%, for the duration of 200 h.     

Study of plasma charging-induced white pixel defect increase in CMOS active pixel sensor

Plasma process-induced “white pixel defect” (WPD) of CMOS active pixel sensor (APS) is studied for Si3N4 spacer etch back process by using a magnetically enhanced reactive ion etching (MERIE) system. WPD preferably takes place at the wafer edge region when the magnetized plasma is applied to Si3N4 etch. Plasma charging analysis reveals that the plasma charge-up characteristic is well matching the edge-intensive WPD generation, rather than the UV radiation. Plasma charging on APS transfer gate might lead to a gate leakage, which could play a role in generation of signal noise or WPD. In this article the WPD generation mechanism will be discussed from plasma charging point of view.     

Step voltage with periodic hold-up etching: A novel porous silicon formation

A novel etching method for preparing light-emitting porous silicon (PS) is developed. A gradient steps (staircase) voltage is applied and hold-up for different periods of time between p-type silicon wafers and a graphite electrode in HF based solutions periodically. The single applied staircase voltage (0–30 V) is ramped in equal steps of 0.5 V for 6 s, and hold at 30 V for 30 s at a current of 6 mA. The current during hold-up time (0 V) was less than 10 μA. The room temperature photoluminescence (PL) behavior of the PS samples as a function of etching parameters has been investigated. The intensity of PL peak is initially increased and blue shifted on increasing etching time, but decreased after prolonged time. These are correlated with the study of changes in surface morphology using atomic force microscope (AFM), porosity and electrical conductance measurements. The time of holding-up the applied voltage during the formation process is found to highly affect the PS properties. On increasing the holding-up time, the intensity of PL peak is increased and blue shifted. The contribution of holding-up the applied steps during the formation process of PS is seen to be more or less similar to the post chemical etching process. It is demonstrated that this method can yield a porous silicon layer with stronger photoluminescence intensity and blue shifted than the porous silicon layer prepared by DC etching.     

Application of inverse problem algorithm for temperature uniformity in rapid thermal processing

This article presents a finite-difference-method formulation to the application of inverse problem algorithms for uniform temperature tracking of several different linear ramp-up rates in rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of silicon wafers are used. The required incident-heat-flux profiles for temperature uniformity across 300-mm-diameter 0.775-mm-thick silicon wafer were intuitively evaluated. Our numerical results indicate that temperature non-uniformity occurring during the ramp increase with the ramp-up rate. Although a linear ramp-up rate of 300 °C/s was used and random errors did reach 3.864 °C, the temperature over the wafer was maintained within 0.665 °C of the wafer center if the incident-heat-flux profiles were dynamically controlled according to the inverse results. These temperature non-uniformities could be acceptable in the advanced rapid thermal processing system.     

二氧化硅纳米颗粒的反应离子刻蚀及其在硅纳米针尖制备中的应用

系统地研究了硅衬底上二氧化硅纳米颗粒的反应离子刻蚀（R IE）过程,并在此基础上制备了可用于场发射的硅纳米针尖阵列.首先,采用改进的蒸发法在硅衬底上实现二氧化硅纳米颗粒的单层密排结构,再采用典型的刻蚀二氧化硅的RIE技术同时刻蚀硅衬底和二氧化硅纳米颗粒,在对纳米颗粒尺寸随刻蚀进行而改变的电镜照片分析的基础上,获得了相应的二氧化硅纳米颗粒刻蚀模型,计算得到横向和纵向的刻蚀速率;当刻蚀后的二氧化硅纳米颗粒从衬底上脱落后,进一步对硅衬底的刻蚀可以得到锐利的硅纳米针尖阵列,初步的实验结果表明,所制备的硅纳米针尖具有较好的场发射特性.     

Plasma/reactor walls interactions in advanced gate etching processes

Wafer-to-wafer reproducibility is a major challenge in gate etching processes. Periodic dry cleaning of the reactor in F-based chemistry between wafers is the most common strategy to ensure process repeatability. However X-ray Photoelectron Spectroscopy analysis of the chamber walls show that this cleaning procedure leaves AlF_x species on the reactor walls, eventually resulting in process drifts and formation of particles. We have thus investigated a new cleaning/conditioning strategy of plasma etching reactors, in which the chamber walls are coated by a carbon-rich film between each wafer, allowing stable processing conditions and highly anisotropic etching profile to be achieved in advanced gate stacks. Finally, we present a new method (based on the detection of Cl₂ by laser absorption) to characterize the reactor walls conditions that could prevent process drifts.     

Heterojunction solar cells with integrated Si and ZnO nanowires and a chalcopyrite thin film

ZnO nanowires (NWs) have been successfully synthesized using a hydrothermal technique on both glass and silicon substrates initially coated with a sputtered ZnO thin film layer. Varying ZnO seed layer thicknesses were deposited to determine the effect of seed layer thickness on the quality of ZnO NW growth. The effect of growth time on the formation of ZnO NWs was also studied. Experimental results show that these two parameters have an important effect on formation, homogeneity and vertical orientation of ZnO NWs. Silicon nanowires were synthesized by a Ag-assisted electroless etching technique on an n-type Si (100) wafer. SEM observations have revealed the formation of vertically-aligned Si NWs with etching depth of ∼700 nm distributed over the surface of the Si. An electron-beam evaporated chalcopyrite thin film consisting of p-type AgGa_0.5In_0.5Se₂ with ∼800 nm thickness was deposited on the n-type ZnO and Si NWs for the construction of nanowire based heterojunction solar cells. For the Si NW based solar cell, from a partially illuminated area of the solar cell, the open-circuit voltage, short-circuit current density, fill factor and power conversion efficiency were 0.34 V, 25.38 mA cm⁻², 63% and 5.50%, respectively. On the other hand, these respective parameters were 0.26 V, 3.18 mA cm⁻², 35% and 0.37% for the ZnO NW solar cell.     

Silicon Wafer Surface-Temperature Monitoring System for Plasma Etching Process

A thermoreflectance temperature measuring system was developed with the aim to realize monitoring of the silicon wafer surface temperature during plasma etching. The thermoreflectance detects variations in temperature through changes in optical reflectance. To overcome such difficulties as low sensitivity and limitation in installation space and position for in situ measurements, the differential thermoreflectance utilizing two orthogonal polarizations was introduced. Noise such as fluctuations in the incident beam intensity or changes of loss in the optical path would affect both polarizations equally and would not affect the measurement. The large angle of incidence of the beam allows measurement to be performed from outside the viewing ports of existing plasma etching process chambers through the gap between the plasma electrode and the silicon wafer. In this article, an off-line measurement result is presented, with results for bare wafers as well as for wafers with metal depositions. A prototype system developed for tests in plasma etching facilities in a production line is described.     

The effects of diffusion coefficient on the etching process of sacrificial oxide layers

The etching rate in hydrofluoric acid (HF) of a sacrificial oxide layer decreases during the extended etching process, as indicated by experiments with temperature from 298 to 308 K at different HF concentration. Existing models indicate that the etching solution's concentration at the etching front decreases during extended etching since the diffusion distance of HF from the source of the solution increases, resulting in the decrease of the etching rate. However, it is found that the measured etching rates do not decrease as seriously as predicted by the models. The difference of etching rate between the experiments and the model can reach as high as 30% for extended etching process. A modified model is proposed to explain this phenomenon by considering the diffusion coefficient of HF as a function of concentration in the solution. In the modified model, the decrease of the HF concentration causes the increase of the HF diffusion coefficient, which will partly compensate the decrease of the concentration caused by the long diffusion distance. In addition, the diffusion coefficient as a function of temperature is also included in the modified model. It is found that the modified model matches well the experimental data.     

Fluid-kinetics enhanced selective etching process of NiPt film by piranha chemistry in silicide formation for complementary metal oxide semiconductor fabrication

NiPtSi is a prime candidate for the complementary metal-oxide-semiconductors CMOS self-aligned silicidation process beyond the 22 nm node. The formation of NiPt silicide in smaller geometries demands more Platinum (Pt) additive to control the silicide quality and a more capable NiPt selective etching process to remove surface residual metals for complementing the formation of silicide. Both higher Pt selective etch rate and lower surface material loss are desired in NiPt selective etching process.High temperature (> 150 °C) sulfuric acid base piranha chemistry in fresh dispensing on wafer can etch Pt with less damage to the exposed wafer surface. By using (1) a larger mass-to-charge density Pt redox reaction zone in the electrochemistry spectrum of the Pt redox behavior, (2) stronger chemical fluid kinetics and (3) intensified voltammetric cycles, the Pt selective removal rate can be boosted. Two types of wet chemical processors are used to examine the fluid-chemical kinetics effect on the Pt selective etching rate. It is shown that higher chemical flow rates and stronger fluid-kinetics can enhance the Pt transport behavior. The collateral wafer surface material loss rate also increases by higher chemical flow rates, but the amount of total material loss actually reduces due to a greater reduction in the required process time. The fluid-kinetics enhanced selective etching process can cover a wider range of NiPt film conditions (5% Pt, up to 200 Å, 10% Pt up to 180 Å).     

Fabrication and characterization of gridded Pt/SiO2/Si MOS structure for hydrogen and hydrogen sulphide sensing

A gridded gate Pt/SiO₂/Si MOS capacitor has been fabricated for detection of Hydrogen (H₂) and Hydrogen Sulphide (H₂S) gases. The MOS device was fabricated on P-type Si <100> (1–6 Ω cm) wafer with thermal oxide layer of thickness about 100 Å, whereas, Platinum (Pt) gate of ∼350 Å was deposited by thermal evaporation technique. The C–V (capacitance vs voltage) and G–V (conductance vs voltage) measurements have been performed for the evaluation of gas sensing behavior of fabricated MOS capacitor structure in H₂ (250–4000 ppm) and H₂S (1000–6000 ppm) gases at both room and 120 °C temperatures, in a closed chamber in air atmosphere. It has been observed that the value of capacitance decreases with increase in gas concentration. The fabricated MOS capacitor sensor has shown better sensitivity towards H₂ (88.6%) at room temperature (∼25 °C) as compared to (∼45%) at 120 °C. Scanning electron microscopy (SEM) and Atomic force microscopy (AFM) studies have revealed the porous nature of the deposited metal film. The side wall diffusion, spillover of Hydrogen into oxide layer, increase in fixed oxide charge density, increase in surface area caused by gridded structure, the formation of dipole layer and change in interface state density on gas exposure, may be the mechanisms of gas sensing for improved sensitivity of the fabricated MOS device.     

Multistage chemical etching for high-precision frequency adjustment in ultrahigh-frequency fundamental quartz resonators

Chemical etching to precisely adjust and to make uniform the thicknesses of vibrating areas of multiple resonators in a single wafer was applied to inverted-mesa quartz resonators exciting an ultrahigh-frequency fundamental thickness vibration. The process consisted of five stages, combining high-rate etching for high productivity and low-rate etching for high-precision adjustment. By using this process, the resonance frequencies of 41 resonators in the single wafer were adjusted to 620 +/- 1.5 MHz, which corresponds to vibrating area thicknesses of 2.2 microm +/- 6 nm. In the temperature-frequency characteristics of these resonators in the single wafer, the difference between the maximum first-order temperature coefficient and the minimum first-order temperature coefficient was equivalent to a cut angle change of two arcminutes. In addition, vibrating areas with an arithmetic mean surface roughness of 0.17 nm on the concave side were produced by this multistage etching.     

大面积高深宽比微结构硅片的热氧化实验研究

利用大面积硅片制作X射线光栅和硅基微通道板等都涉及硅的热氧化工艺。热氧化使具有高深宽比微结构的大面积硅片产生形变,严重影响了这些器件的应用。本文以5英寸硅片为例,研究了硅基微结构在热氧化过程中的变形问题,定性分析了产生形变的力学因素,提出了减小形变的氧化方法。首先实验制作了具有高深宽比微结构的硅片,采用不同的氧化方法,比较了变形的大小。结果表明,通过控制热氧化过程中的温度来控制热膨胀系数和在热氧化过程中施加外部热塑应力等方法能够有效地减小热氧化变形量。     

Catalytic synthesis of ZnO nanorods on patterned silicon wafer—An optimum material for gas sensor

ZnO nanorods have been synthesized over etch-patterned Si (110) wafer using annealed silver thin film as growth catalyst. The growth of ZnO nanorods were performed by a two-step process. Initially, the deposition of Zn thin film was done on the annealed silver catalyst film over etch-patterned Si (110) substrate by thermal evaporation, and then annealed at 800°C in air. The etching of the patterned Si (110) wafers was carried out by 50% aqueous KOH solution. The samples were investigated by optical microscopy, scanning electron microscopy, X-ray diffraction, Raman spectroscopy and room temperature photoluminescence spectroscopy. ‘V’ shaped grooves with no undercut were formed after etching due to the anisotropic nature of the KOH etchant. The etch-patterned wafer was used to provide larger surface area for ZnO growth by forming ‘V’-grooves. This ZnO film may be predicted as a very good material for gas sensor.     

Formation of In nanoparticles on InP wafers by laser-assisted etching

Indium nanoparticles were formed by laser etching an InP (100) wafer in a 10% chlorine–helium atmosphere maintained at ~5–8 × 10⁻⁵ Torr. The wafer was irradiated by a homogenized ultraviolet beam with a series of 50–4500 pulses at a fluence of 230 mJ/cm². The surface was also irradiated using fluences from 50 to 340 mJ/cm² with 600 pulses. The irradiated surfaces were studied using scanning electron microscopy (SEM), energy dispersive spectroscopy (EDS), and Raman spectroscopy. Raman spectroscopy confirmed that the irradiated surface layer remains crystalline. According to EDS analysis, the surface particles are composed primarily of indium. SEM images show that the number of pulses and the pulse intensity can control the size distribution of the particles.     

An Effective Emissivity Model for Rapid Thermal Processing Using the Net-Radiation Method

A reflective shield has been placed in the lower chamber of some rapid thermal processing (RTP) systems so that the temperature of the silicon wafer can be accurately measured in situ with light-pipe radiometers. Better knowledge of the effective emissivity of the wafer reduces the uncertainty in the temperature measurement. This paper describes an enclosure model based on the net-radiation method for predicting the effective emissivity of the wafer. The model treats the surfaces in the enclosure as diffuse emitters, with a reflectivity that may include a diffuse component and a specular component. Using this model, a parametric study is performed to investigate the influence of the geometric arrangement, surface temperature and properties, and wavelength on the effective emissivity. The algorithm developed in this work may serve as a tool to improve radiometric temperature measurement in RTP systems.     

Reliability study of through-silicon via (TSV) copper filled interconnects

Through-silicon vias (TSVs) have been extensively studied because of their ability to achieve chip stacking for enhanced system performance. The fabrication process is becoming somewhat mature. However, reliability issues need to be addressed in order for an eventual transition from laboratory to production. In our laboratory, vias with tapered sidewalls are formed through a modified Bosch process using deep reactive ion etching (DRIE). Vias are lined with silicon dioxide using plasma enhanced chemical vapor deposition (PECVD) followed by sputter deposited titanium barrier and copper seed layers before filling with a reverse pulse copper electroplating process. Following attachment of the process wafer to a carrier wafer, the process wafer is thinned from the backside by a combination of mechanical methods and reactive ion etching (RIE). Fabricated vias are subjected to thermal cycling with temperatures ranging from − 25 °C to 125 °C. For via chains, erratic changes in resistance upon temperature cycling indicated a problem with the wire bonds used to connect the sample to the test fixture. Test methods were modified to avoid wire bonding and form the basis of reliability studies presented in this paper. TSVs are shown to be stable with small increases in measured resistance for 200 cycles. In addition, small changes in resistance are observed when vias are held at elevated temperatures for extended periods of time.     

Bi-stable pore size during electrochemical etching of n-type silicon during a thermal ramp

We have investigated the change in size and density of pores during electrochemical etching of n-type (5 Ωcm) silicon under backside illumination and subjected to a thermal ramp. The pore structure was allowed to self organize, and for the parameters reported here this results in macropores with diameters in the ∼ μm order of magnitude range. As the etching progressed under constant current conditions, the electrolyte and the sample heated slowly up in the temperature range 20-60 °C. The resulting pore structure was obtained by scanning electron microscope examination of cross sections of cleaved samples. The temperature ramp caused the pore diameters and pore densities to change abruptly rather than continuously. The change can thus phenomenologically be described as a transition between two stable pore size configurations; bi-stable switching or phase transition. This phenomenon is observed for a range of parameters yielding macropores: current densities between 2-20 mA/cm² and varying light intensity. The transition is between known configurations.     

Modelling of semiconductor wafer fabrication systems by extended object-oriented Petri nets

In this paper, extended object-oriented Petri nets (EOPNs) are proposed for the effective modelling of semiconductor wafer fabrication systems (SWFSs). To cope with their complexity in terms of the re-entrant process route and the mixed production mode, a special type of transition called main-bus gate is introduced, which may lead each kind of product to undergo every re-entrant processing stage. In addition, the hierarchical approach is also applied to cope with the complexity. An etching area that processes 0.25?µm logic IC products is taken as an illustration to present the detailed modelling procedures by EOPNs, and the resulting model validates that the EOPNs may cope well with complex SWFSs modelling.     

Chemical etching of InP (1 0 0) wafer based on a volcanic mineral water

We have successfully demonstrated that a solution of spa water [Tamagawa Spa water (TaSW):H₂O₂ = 1:1] etches InP (1 0 0) wafer. The TaSW is a colorless acidic liquid of pH ∼1.1. It contains a considerable amount of positive ions, such as H⁺, Al³⁺, and Ca²⁺. The Cl⁻, HSO₄²⁻, and SO₄²⁻ ions are the main anions. The TaSW-etchant system provides shiny flat surfaces on the etched bottoms. The spa-etchant system has reproducible etching rates and does not erode photoresist masks. The etching kinetics is reaction-rate limited. The spa-etchant system is also found to etch GaAs (1 0 0) wafer, but the etched surface is considerably roughened.