Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption

To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UML-based hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS cannot only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods.     

基于遗传算法的可重构系统软硬件划分

在考虑动态部分重构及重构延时等特征的基础上,采用遗传算法及其与爬山算法的融合实现可重构系统软硬件任务的划分,并采用动态优先级调度算法进行划分结果的评价。实验表明,在可重构系统的资源约束等条件下,算法能够有效地实现应用任务图到可重构系统的时空映射。     

动态重构硬件加速中的性能开销建模

近年来,随着可重构计算方法和可重构硬件特性的不断演进,基于FPGA动态部分重构技术构建运行时可重构加速器已经成为解决传统加速器设计中硬件资源限制问题的重要途径.然而,区别于传统静态重构加速器,FPGA的动态重构开销是影响硬件加速整体性能的重要因素,而目前尚缺少能够在可重构硬件设计的早期阶段进行动态重构开销精确估算的相关...     

可重构资源管理及硬件任务布局的算法研究

可重构系统具有微处理器的灵活性和接近于ASIC的计算速度,可重构硬件的动态部分重构能力能够实现计算和重构操作的重叠,使系统能够动态地改变运行任务,可重构资源管理和硬件任务布局方法是提高可重构系统性能的关键.提出了基于任务上边界计算最大空闲矩形的算法(TT-KAMER),能够有效地管理系统的空闲可重构资源;在此基础上使用FF和启发式BF算法进行硬件任务的布局.实验表明,算法能够有效地实现在线资源分配与任务布局,获得较高的资源利用率.     

动态部分重配置及其FPGA实现

动态部分重配置充分利用了FPGA芯片提供的可重配置功能，提高了FPGA芯片的利用率，减小了FPGA芯片的配置时间，有效地提高了系统的整体性能。该文介绍了动态部分重配置的两种实现方法，并在Spartan-II FPGA上进行了验证。     

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.     

Energy efficient processing of motion estimation for embedded multimedia systems

Visual sensor networks require low power compression techniques of large amount of video data in each camera node due to the energy-constrained and bandwidth-limited environments. In this paper, energy-efficient architecture for Variable Block Size Motion Estimation is proposed to fully utilize dynamic partial reconfiguration capability of programmable hardware fabric in distributed embedded vision processing nodes. Partial reconfiguration of FPGA is exploited to support run-time reconfiguration of the proposed modular hardware architecture for motion estimation. According to the required search range, hardware reconfiguration is performed adaptively to reduce the hardware resources and power consumption. A reconfigurable ME ranging from simple 1-D to a complex 2-D Sum of Absolute Differences (SAD) array to perform full search block matching is selected in order to support different search window size. The implemented scalable SAD array can provide different resolutions and frame rates for real time applications with multiple reconfigurable regions.     

基于最大空闲矩形的可重构资源管理方法

可重构硬件如FPGA的规模和集成度的提高使其承载的硬件任务越来越多,FPGA的动态部分重构能力使任务可在系统运行过程中动态地添加或者删除而不影响其他任务的运行,对可重构硬件的资源管理非常重要。该文提出一种基于任务上边界计算最大空闲矩形的算法,使用这些最大空闲矩形能够有效地管理可重构资源,便于更好地利用具有动态部分重构能力的可重构硬件。     

Run-time generation of partial FPGA configurations

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.     

A prefetch-aware scheduling for FPGA-based multi-task graph systems

The Journal of Supercomputing - In partially run-time reconfigurable (PRR) FPGAs, hardware tasks should be configured before their execution. The configuration delay imposed by the reconfiguration...     

OCEAN,a flexible adaptive Network-On-Chip for dynamic applications

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed.     

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

Current multimedia applications are characterized by highly dynamic and non-deterministic behaviour as well as high-performance requirements. Potentially, partially reconfigurable fine-grain configurable architectures like FPGAs can be reconfigured at run-time to match the dynamic behaviour. However, the lack of programming support for dynamic task placement as well as the large configuration overhead has prevented their use for highly dynamic applications. To cope with these two problems, we have adopted an FPGA model with specific support for task allocation. On top of this model, we have applied an existing hybrid design-time/run-time scheduling flow initially developed for multiprocessor systems. Finally, we have extended this flow with specific modules that greatly reduce the reconfiguration overhead making it affordable for current multimedia applications.     

基于FPGA的动态可重配置短波收发机

使用基于模块化的动态部分重配置技术,构建了基于FPGA的动态可重配置软件无线电系统平台,并在该平台上设计了动态可重配置MIL-STD-188-110B短波收发机系统。与传统的全局静态重配置系统相比,动态可重配置系统扩展性好,配置速度快,用于存储配置比特流所需的空间较少,配置控制方式比较灵活。     

一种面向动态可重构计算的调度算法

硬件任务的调度是影响动态可重构系统性能的关键因素之一.提出一种任务间最小空隙调度算法MGS(minimum gap scheduling algorithm),该算法借助任务投影和调度代价函数,采用二维时空坐标系协调各硬件任务占用的芯片资源和执行时间,可有效减少系统资源浪费,提高并行度.MGS算法策略直观,调度开销小,且同时适用于实时和非实时场合.仿真实验表明,与已有算法相比,MGS算法不但降低了硬件任务的调度时间开销,而且具有更高的芯片利用率和更低的任务拒绝率.     

Design space exploration for partially reconfigurable architectures in real-time systems

In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area improvement up to 38% on some resources without compromising application performance, in a very small amount of time: less than 30 s.     

硬件内部进化原理及其实现

研究了如何实现硬件的内部进化;讨论了实现硬件内部进化的3个条件：物质基础RCl000板卡、进化算法HereBoy和实时重构接口JBits;给出了硬件内部进化的具体流程,其实质是采用JBits对RC1000板卡上的FPGA进行实时部分重构;实例证明基于JBitsAPI、RCl000板卡和遗传算法实现硬件内部进化是可行的;对不同编码方法及不同进化资源条件下,收敛速度加以比较,结果表明：采用多参数级联编码法,协同进化LUT及其连线,显著改善了收敛速度。     

DR-TCP: Downloadable and reconfigurable TCP

Advances in communication technology allow a variety of new network environments and services available very rapidly. Appearance of various network environments tends to enable a user with a mobile terminal to access among different network simultaneously. However, since new network environment affects performance of communication protocols, terminal systems should provide adaptation schemes for the protocols in order to keep the quality of network performance high. A possible solution is to make the protocol reconfigurable to be adapted to current network environment. Unfortunately, because most existing network systems are implemented monolithically, they cannot support protocol reconfiguration dynamically at runtime.This paper proposes a new reconfigurable model that enables TCP functions to be adapted whenever network environment is changed. The proposed scheme also supports binary-level protocol upgrade for extensibility by downloading new TCP variants which the terminal does not have for new network environment, and it is more suitable for mobile hand-held devices than existing source-level solution. Our model is based on a recursive state machine. We re-implement TCP Reno from scratch using our proposed model. The new implementation of TCP Reno is named DR-TCP. To demonstrate the effectiveness of DR-TCP, dynamic reconfiguration is performed over Internet, which successfully converts DR-TCP to TCP Westwood at runtime.     

可重构安全系统建模与配置生成方法研究

以安全重构元为基础,能够提供高灵活性、适应性和可扩展性安全服务的可重构安全计算系统已成为当前安全研究领域的热点问题.目前,关于重构机理的研究主要采取基于功能候选集的静态重构配置生成方法,可重构安全系统作为一种主动安全防御手段,应具有动态自动重构的能力,避免人工介入导致的脆弱性.针对动态自动可重构安全系统的建模以及配置生成过程的描述问题,提出了一种基于直觉主义逻辑扩展的动态自动可重构安全系统逻辑模型SSPE,给出了逻辑模型SSPE上的语法和推理规则,设计了基于SSPE的等级化安全重构元和安全需求建模和表达方法,并给出了基于映射关系的安全重构元描述向逻辑语言的转换规则.最后,以IPSec协议为例,阐述了可重构安全系统重构配置的动态自动推理生成过程.基于直觉主义逻辑的可重构安全系统建模和配置生成方法,为研究可重构安全系统的重构机理提供了新的思路和方法,具有重要的意义.     

可重构系统的调度算法研究

根据重构系统的需要,提出了一种适合动态可重构系统的混合调度映射算法。采用图分割理论的方式对任务进行描述,并建立了动态可重构模式。该算法是一种在可重构硬件平台上多核应用的混合调度映射算法,即将每一个应用程序看作一个程序核,利用程序核之间的相关信息,尽可能减少可重构造成的系统时间开销。实验结果证明,所提出的算法能够有效地完成图分割到可重构系统的时空映射,与其他算法相比性能较高。     

可重构密码处理结构中重构机制及对性能的影响

重构机制对可重构密码处理系统的性能有着重要的影响,该文从全局、局部、静态、动态几方面提出了流水化可重构密码处理结构中重构机制的分类,给出了各种机制的吞吐率和延迟公式,并分析了几种机制的性能和实现代价,最后给出了在采用局部动态重构机制的可重构密码处理结构中密码处理的性能。