Device characteristics of amorphous indium gallium zinc oxide thin film transistors with ammonia incorporation

The effect of ammonia gas on amorphous indium gallium zinc oxide thin film transistors is investigated. The ammonia is incorporated into the sputtered a-IGZO film during the deposition process. The results indicate that the sub-threshold swing of the NH₃ incorporated TFTs is significantly improved from 2.8 to 1.0 V/decade, and the hysteresis phenomenon is also suppressed during the forward and reverse sweeping measurement. By X-ray photoelectron spectroscopy analyses, Zn-N and O-H bonds are observed in ammonia incorporated a-IGZO film. Therefore, the improvements in the electrical performance of TFTs are attributed to the passivation of dangling bonds and/or defects by ammonia.     

氧分压对铟镓锌氧薄膜晶体管性能影响

采用标准的液晶显示屏基板制备工艺制备出铟镓锌氧薄膜晶体管(IGZO-TFT),通过调节IGZO薄膜工艺中氧分压,研究不同氧分压对TFT器件电学性能的影响。实验结果表明,所有器件都展现出良好的电学特性,随着氧分压从10%增加到50%,TFT的阈值电压由0.5 V增加到2.2 V,而亚阈值摆幅没有发生变化。在栅极施加30 V偏压3600 s后,随着氧分压的增加,阈值电压向正向的漂移量由1 V增加到9 V。经过分析得出高氧分压的IGZO-TFT器件中载流子浓度低,建立相同导电能力的沟道时所需要栅极电压会更大,阈值电压会增加。而在金属-绝缘层-半导体(MIS)结构中低载流子浓度会导致有源层能带弯曲的部分包含更多与电子陷阱相同的能态,栅介质层(GI)会俘获更多的电子,造成阈值电压漂移量较大的现象。     

High performance low temperature metal-induced unilaterallycrystallized polycrystalline silicon thin film transistors forsystem-on-panel applications

Thin film transistors (TFTs) with low-temperature processed metal-induced laterally crystallized (MILC) channels and self-aligned metal-induction crystallized (MIC) source and drain regions have been demonstrated recently as potential devices for realizing electronics on large-area, inexpensive glass panels. While these TFTs are better than their solid-phase crystallized counterparts in many device performance measures, they suffer from higher off-state leakage current and early drain breakdown. A new technology is proposed, employing metal-induced-unilateral crystallization (MIUC), which results in the removal from the edges of and within the channel region all major grain boundaries transverse to the drain current flow. Compared to the conventional “bilateral” MILC TFTs, the new MIUC devices are shown to have higher field-effect mobility, significantly reduced leakage current, better immunity to early drain breakdown, and much improved spatial uniformity of the device parameters. Thus they are particularly suitable for realizing low temperature CMOS systems on inexpensive glass panels     

Influence of rapid thermal and low temperature processing on theelectrical properties of polysilicon thin film transistors

In this paper rapid thermal processing (RTP) is studied for the crystallization and oxidation of deposited silicon layers. The purpose is to present and compare the results obtained by RTP, low temperature processing (LTP), or a combination of both, for the fabrication of polycrystalline silicon thin film transistors (poly-TFT's). The polysilicon and polyoxide are obtained by low thermal annealing, oxidation (LTA, O) and/or rapid thermal annealing, oxidation (RTA, O) of amorphous silicon films deposited from disilane at a temperature of 465°C. For the Si films annealed at 750°C or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobilities are increased. We suggest that there is a correlation between the optical extinction coefficient k (at λ=405 nm), the potential barrier height Φ_B due to the grains, and the field-effect mobility, μ_n,p, of the polysilicon film. This correlation indicates that the polysilicon film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains. Moreover, it appears that the large amount of crystalline defects remaining in the so-called “grains” of the films annealed at 600°C (LTA) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFT's electrical characteristics, the work suggests combining RT and LT steps to obtain TFT's with improved electrical performance     

Water-enhanced negative bias temperature instability in p-type low temperature polycrystalline silicon thin film transistors

Water-enhanced degradation of p-type low temperature polycrystalline silicon thin film transistors under negative bias temperature (NBT) condition is studied. H₂O penetration into gate oxide network and the role of H₂O during NBT stress are confirmed and clarified respectively. To prevent H₂O diffusion, a combination of a layer of PECVD SiO₂ and a layer of PECVD Si₃N₄ as passivation layers are investigated, revealing that 100 nm SiO₂ and 300 nm Si₃N₄ can effectively block H₂O diffusion and improve device NBT reliability.     

Low-frequency noise in low temperature unhydrogenated polysilicon thin film transistors

Low-frequency noise measurements are performed in two types of low temperature polysilicon thin film transistors (TFTs). For the first TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility fluctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the fluctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite different from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering.     

Influence of thermal annealing on electrical and optical properties of indium tin oxide thin films

Transparent conducting indium tin oxide (ITO) thin films with the thickness of 300 nm were deposited on quartz substrates via electron beam evaporation, and five of them post-annealed in air atmosphere for 10 min at five selected temperature points from 200 °C to 600 °C, respectively. An UV–vis spectrophotometer and Hall measurement system were adopted to characterize the ITO thin films. Influence of thermal annealing in air atmosphere on electrical and optical properties was investigated in detail. The sheet resistance reached the minimum of 6.67 Ω/sq after annealed at 300 °C. It increased dramatically at even higher annealing temperature. The mean transmittance over the range from 400 nm to 800 nm reached the maximum of 89.03% after annealed at 400 °C, and the figure of merit reached the maximum of 17.79 (Unit: 10⁻³ Ω⁻¹) under the same annealing condition. With the annealing temperature increased from 400 °C to 600 °C, the variations of transmittance were negligible, but the figure of merit decreased significantly due to the deterioration of electrical conductivity. With increasing the annealing temperature, the absorption edge shifted towards longer wavelength. It could be explained on the basis of Burstein–Moss shift. The values of optical band gap varied in the range of 3.866–4.392 eV.     

Magnetron-sputtered high performance Y-doped ZnO thin film transistors fabricated at room temperature

In this report, sputtered-grown undoped ZnO and Y-doped ZnO (ZnO:Y) thin film transistors (TFTs) are presented. Both undoped ZnO and ZnO:Y thin films exhibited highly preferred c-axis oriented (002) diffraction peaks. The ZnO:Y thin film crystallinity was improved with an increase of (002) peak intensity and grain size. The electrical properties of ZnO:Y TFTs were significantly enhanced relative to undoped ZnO TFTs. ZnO:Y TFTs exhibited excellent performance with high mobility of 38.79 cm² V⁻¹ s⁻¹, small subthreshold swing of 0.15 V/decade, and high I_on/I_off current ratio of the order of 8.17 × 10⁷. The O_1s X-ray photoelectron spectra (XPS) showed oxygen vacancy-related defects present in the ZnO:Y TFTs, which contributed to enhancing the mobility of the TFTs.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

Impact of light soaking and thermal annealing on amorphous silicon thin film performance

Nowadays, there is a wide debate in literature related to the silicon thin films seasonal performance. Amorphous modules seem to react positively to the temperature, while the temperature parameters indicate a negative thermal response. Periodic fluctuations of nominal power due to light soaking and thermal annealing effects are observed. On the other hand, the module temperature reached in some open rack plants seems too low to activate annealing power regeneration process so that the seasonal performance trend may depend mainly on other effects such as spectral or irradiance. In the following paper, a model that allows to calculate the impact of all the phenomena that affect the photovoltaic performance is used. The light soaking and thermal annealing contributions are measured from outdoor data using two different methods. Both methods lead to similar results, and the model is able to reproduce the seasonal performance with an acceptable level of reliability on the day, hour, minute time scale. An analysis of each effect contribution to the seasonal performance is also provided. Thus, main open questions related to a‐Si thin films performance such as positive reaction to temperature and seasonal fluctuations are discussed. Copyright © 2015 John Wiley & Sons, Ltd.     

高性能钆铝锌氧薄膜晶体管的制备

本文研究并制备了钆铝锌氧薄膜和以钆铝锌氧为有源层的薄膜晶体管。钆铝锌氧薄膜材料的光致发光光谱和透过率说明钆铝锌氧薄膜在透明显示方向的应用潜力。透射电子显微镜揭示了钆铝锌氧薄膜的非晶态微观结构。钆铝锌氧薄膜晶体管显示了良好的转移特性和输出特性。器件开关比大于10~5、饱和迁移率约为10cm~2·V~(-1)·s~(-1)。实验结果表明,钆铝锌氧薄膜可用作氧化物薄膜晶体管的有源层材料;钆铝锌氧薄膜晶体管可作为像素电路的驱动器件。     

Improved performance in n-channel organic thin film transistors by nanoscale interface modification

We demonstrate that the electrical properties of n-channel thin film transistors can be enhanced by inserting a nanoscale interfacial layer, namely, cesium carbonate (Cs₂CO₃), between organic semiconductor and source/drain electrodes. Devices with the Cs₂CO₃/Al electrode showed a reduction of contact resistance, not only with respect to Al, but also compared to Ca. The improvement is attributed to the reduction in the energy barrier of electron injection and the prevention of unfavorable chemical interaction between the organic layer and the metal electrode. High field-effect mobility of 0.045 cm²/V s and on/off current ratios of 10⁶ were obtained in the [6,6]-phenyl C60 butyric acid methyl ester-based organic thin film transistors using the Cs₂CO₃/Al electrodes at a gate bias of 40 V.     

铜铟镓硒薄膜太阳电池研究进展和挑战

铜铟镓硒(Cu（In,Ga）Se₂,CIGS)太阳电池产业化受到全世界广泛关注。作为高转换效率薄膜电池,其效率可与晶硅电池相比,目前最高效率达到23.35%。对于小面积实验室电池而言,研究重点是精确控制吸收层的化学计量比和效率;对于工业化生产而言,除化学计量比和效率外,成本、重现性、产出和工艺兼容性在商业化生产中至关重要。重点介绍了不同制备工艺、吸收层组分梯度调控、碱金属后沉积处理、宽带隙无镉缓冲层、透明导电层和柔性衬底等研究进展。从CIGS电池的效率来看,将实验室创纪录的高效电池技术转移到平均工业生产水平带来显而易见的挑战。     

铟掺杂显著改善硫化锌薄膜光电性能研究

Abstract： This paper reports a new material, indium-doped ZnS （ZnS：In） film, which is fabricated for the first time to improve its electrical and optical performance. By electron beam evaporation technology and the optimized annealing treatment, high quality ZnS：In film is prepared. XRD indicates that the incorporation of 6 at.% indium atoms into ZnS film causes little lattice deformation. The AFM results imply that large sized particles are compactly dispersed in the ZnS：In layer and results in an unsmooth surface. Electrical and optical property tests show that the resistivity of ZnS film is greatly decreased to 4.46×10-2 Ω.cm and the optical transmittance is improved to 85% in the visible region. Comparing with the results in other literatures, significant progress in electrical/optical performance has been made in this paper.     

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN_x/SiO₂ gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN_x/SiO₂) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (ΔV_TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.     

基板温度对氧化锌薄膜晶体管性能的影响

以ITO玻璃为衬底,利用射频磁控溅射制备了以氧化硅为绝缘层的氧化锌薄膜晶体管。研究了氧化锌薄膜制备过程中不同的衬底温度（衬底温度分别为室温、100℃ 和200℃）对于器件性能的影响。和室温下制备的氧化锌薄膜晶体管相比,衬底温度200℃条件下制备的器件的场效应迁移率提高了94% （从1.6cm2/Vs 提高至3.11cm2/Vs）,亚阈值摆幅 从2.5V/dec 降低至1.9 V/dec 而且阈值电压漂移也从18V 减小至3V （老化电压为25V的正栅压,老化时间为1小时）。实验结果表明,衬底加热对于氧化锌薄膜晶体管的迁移率、亚阈值摆幅和偏压稳定性有明显的影响。利用原子力显微镜AFM对氧化锌薄膜的特性就行了研究,器件性能提高的原因也在文中进行了阐述。     

Influence of substrate temperature on the performance of zinc oxide thin film transistor

Top-contact thin film transistors（TFTs） using radio frequency（RP） magnetron sputtering zinc oxide （ZnO） and silicon dioxide（SiO₂） films as the active channel layer and gate insulator layer,respectively,were fabricated.The performances of ZnO TFTs with different ZnO film deposition temperatures（room temperature, 100℃and 200℃） were investigated.Compared with the transistor with room-temperature deposited ZnO films, the mobility of the device fabricated at 200℃is improved by 94%and the threshold voltage shift is reduced from 18 to 3 V（after 1 h positive gate voltage stress）.Experimental results indicate that substrate temperature plays an important role in enhancing the field effect mobility,sharping the subthreshold swing and improving the bias stability of the devices.Atomic force microscopy was used to investigate the ZnO film properties.The reasons for the device performance improvement are discussed.     

Crack-guided effect on dynamic mechanical stress for foldable low temperature polycrystalline silicon thin film transistors

In the thin film transistors (TFTs) device research for foldable display, the degradation effect by the mechanical stress is crucial. Here, the crack position is critical for TFT reliability. However, it is difficult to characterize the crack position due to the random generation of the crack by mechanical stress. In this paper, the crack-guided low temperature polycrystalline silicon (LTPS) TFT test structures are fabricated and the crack-guided effects on mechanical stress of the tested TFT structure are analyzed. To strain on the foldable LTPS TFTs, 50,000 cycles of tensile and parallel direction dynamic mechanical stresses were applied with 2.5-mm bending radius. Based on the results, the generating crack position can be guided and controlled and also TFT reliability for foldable display can be enhanced.