Impact of level-2 cache sharing on the performance and power requirements of homogeneous multicore embedded systems

In order to satisfy the needs for increasing computer processing power, there are significant changes in the design process of modern computing systems. Major chip-vendors are deploying multicore or manycore processors to their product lines. Multicore architectures offer a tremendous amount of processing speed. At the same time, they bring challenges for embedded systems which suffer from limited resources. Various cache memory hierarchies have been proposed to satisfy the requirements for different embedded systems. Normally, a level-1 cache (CL1) memory is dedicated to each core. However, the level-2 cache (CL2) can be shared (like Intel Xeon and IBM Cell) or distributed (like AMD Athlon). In this paper, we investigate the impact of the CL2 organization type (shared Vs distributed) on the performance and power consumption of homogeneous multicore embedded systems. We use VisualSim and Heptane tools to model and simulate the target architectures running FFT, MI, and DFT applications. Experimental results show that by replacing a single-core system with an 8-core system, reductions in mean delay per core of 64% for distributed CL2 and 53% for shared CL2 are possible with little additional power (15% for distributed CL2 and 18% for shared CL2) for FFT. Results also reveal that the distributed CL2 hierarchy outperforms the shared CL2 hierarchy for all three applications considered and for other applications with similar code characteristics.     

Improving the computational efficiency of modular operations for embedded systems

Security protocols such as IPSec, SSL and VPNs used in many communication systems employ various cryptographic algorithms in order to protect the data from malicious attacks. Thanks to public-key cryptography, a public channel which is exposed to security risks can be used for secure communication in such protocols without needing to agree on a shared key at the beginning of the communication. Public-key cryptosystems such as RSA, Rabin and ElGamal cryptosystems are used for various security services such as key exchange and key distribution between communicating nodes and many authentication protocols. Such public-key cryptosystems usually depend on modular arithmetic operations including modular multiplication and exponentiation. These mathematical operations are computationally intensive and fundamental arithmetic operations which are intensively used in many fields including cryptography, number theory, finite field arithmetic, and so on. This paper is devoted to the analysis of modular arithmetic operations and the improvement of the computation of modular multiplication and exponentiation from hardware design perspective based on FPGA. Two of the well-known algorithms namely Montgomery modular multiplication and Karatsuba algorithms are exploited together within our high-speed pipelined hardware architecture. Our proposed design presents an efficient solution for a range of applications where area and performance are both important. The proposed coprocessor offers scalability which means that it supports different security levels with a cost of performance. We also build a system-on-chip design using Xilinx’s latest Zynq-7000 family extensible processing platform to show how our proposed design improve the processing time of modular arithmetic operations for embedded systems.     

Improving the performance of distributed virtual environment systems

The last years have witnessed a dramatic growth in the number as well as in the variety of distributed virtual environment systems. These systems allow multiple users, working on different client computers that are interconnected through different networks, to interact in a shared virtual world. One of the key issues in the design of scalable and cost-effective DVE systems is the partitioning problem. This problem consists of efficiently assigning the existing clients to the servers in the system and some techniques have been already proposed for solving it. This paper experimentally analyzes the correlation of the quality function proposed in the literature for solving the partitioning problem with the performance of DVE systems. Since the results show an absence of correlation, we also propose the experimental characterization of DVE systems. The results show that the reason for that absence of correlation is the nonlinear behavior of DVE systems with regard to the number of clients in the system. DVE systems reach saturation when any of the servers reaches 100 percent of CPU utilization. The system performance greatly decreases if this limit is exceeded in any server. Also, as a direct application of these results, we present a partitioning method that is targeted to keep all the servers in the system below a certain threshold value of CPU utilization, regardless of the amount of network traffic. Evaluation results show that the proposed partitioning method can improve DVE system performance, regardless of both the movement pattern of clients and the initial distribution of clients in the virtual world.     

Study of the performance impact of a cache buffer in solid-state disks

An SSD generally has a small memory, called cache buffer, to increase its performance and the frequently accessed data are maintained in this cache buffer. These cached data must periodically write back to the NAND Flash memory to prevent the data loss due to sudden power-off, and it should immediately flush all dirty data items into a non-volatile storage media (i.e., NAND Flash memory), when receiving a flush command, while the flush command is supported in Serial ATA (SATA) and Serial Attached SCSI (SAS). Thus, a flush command is an important factor to give significant impact on SSD performance.In this paper, we have investigated the impact of a flush command on SSD performance and have conducted in-depth experiments with versatile workloads, using the modified FlashSim simulator. Our performance measurements using PC and server workloads provide several interesting conclusions. First, a cache buffer without a flush command could improve SSD performance as a cache buffer size increases, since more requested data could be handled in the cache buffer. Second, our experiments have revealed that a flush command might give a negative impact on SSD performance. The average response time per request with a flush command is getting worse compared to not supporting the flush command, as cache buffer size increases. Finally, we have proposed the backend flushing scheme to nullify the negative performance impact of the flush command. The backend flushing scheme first writes the requested data into a cache buffer and sends the acknowledgment of the request completion to a host system. Then, it writes back the data in the cache buffer to NAND Flash memory. Thus, the proposed scheme could improve SSD performance since it might reduce the number of the dirty data items in a cache buffer to write back to NAND Flash memory.All these results suggest that a flush command could give a negative impact on SSD performance and our proposed backend flushing scheme could improve the SSD performance while supporting a flush command.     

一类非线性对象基于区间观测器的L2增益性能综合

本文针对一类非线性系统,首次考虑了基于区间观测器的L2增益性能控制器设计问题.该控制器的设计主要分两个步骤:首先,设计了该非线性系统的区间观测器,使得观测器系统与原系统之间的误差系统为单调系统;然后,基于该区间观测器系统设计了观测器状态反馈控制律,使得相应的闭环系统为渐近稳定且具有L2增益性能.最后,仿真数例表明了本文所提出方法的有效性.     

Improving performance of HMM-based off-line signature verification systems through a multi-hypothesis approach

The neural and statistical classifiers employed in off-line signature verification (SV) systems are often designed from limited and unbalanced training data. In this article, an approach based on the combination of discrete Hidden Markov Models (HMMs) in the ROC space is proposed to improve the performance of these systems. Inspired by the multiple-hypothesis principle, this approach allows the system to select, from a set of different HMMs, the most suitable solution for a given input sample. By training an ensemble of user-specific HMMs with different number of states and different codebook sizes, and then combining these models in the ROC space, it is possible to construct a composite ROC curve that provides a more accurate estimation of system performance. Moreover, in testing mode, the corresponding operating points—which may be selected dynamically according to the risk associated with input samples—can significantly reduce the error rates. Experiments performed by using a real-world off-line SV database, with random, simple and skilled forgeries, indicate that the multi-hypothesis approach can reduce the average error rates by more than 17%, as well as the number of HMM states by 48%.     

Evaluating the performance of FFT library implementations on modern hybrid computing systems

The Journal of Supercomputing - Fast Fourier transform is widely used to solve numerous scientific and engineering problems. In particular, this transform is behind the software dealing with speech...     

Improving performance and determinism of multitasking systems on the LEON architecture

Real-time systems are characterised by the fact that they have to meet a set of both functional and temporal requirements. Processor architectures have a significant impact on the predictability of software execution times and can add different sources of indeterminism depending on the features provided. The LEON processor family is the reference platform for space missions of the European Space Agency, with open-source implementations that are written in VHDL language. All versions of the LEON processors conform to the SPARC architecture Version 8. This architecture groups the general-purpose registers into windows to reduce memory transfer overhead in function calls. Unfortunately, this mechanism introduces indeterminism in software execution times at various levels. In this paper, we propose an extension to the original architecture that provides determinism for a configurable subset of tasks and interrupt service routines and eliminates the concurrency-related jitter, all this with a minimum cost in terms of FPGA resource utilisation. For the validation of the proposed solution, we have implemented the extension into the VHDL code of the LEON3 processor and modified the source code of the RTEMS operating system to make use of the new functionality.     

Strategic planning of information systems at the corporate level

Strategic issues related to information systems are subject to conflicting trends. One is the more rapid change in environmental factors; the other is the growing complexity of requests that reduce the rate of response. This study examines the basis for concern about current issues. The factors are reviewed in the light of recently published material. Three organizational structures for information system planning are compared in terms of their ability to meet different organizational requirements. Techniques which have been used successfully in the definition of strategic issues and analysis of environmental factors are presented. The object is to aid the integration of information system strategies into the overall strategy of an enterprise.     

Improving transient performance of adaptive control via a modified reference model and novel adaptation

This paper presents a new model reference adaptive control (MRAC) framework for a class of nonlinear systems to address the improvement of transient performance. The main idea is to introduce a nonlinear compensator to reshape the closed‐loop system transient, and to suggest a new adaptive law with guaranteed convergence. The compensator captures the unknown system dynamics and modifies the given nominal reference model and the control action. This modified controlled system can approach the response of the ideal reference model. The transient is easily tuned by a new design parameter of this compensator. The nominal adaptive law is augmented by new leakage terms containing the parameter estimation errors. This allows for fast, smooth and exponential convergence of both the tracking error and parameter estimation, which again improves overall reference model following. We also show that the required excitation condition for the estimation convergence is equivalent to the classical persistent excitation (PE) condition. In this respect, this paper provides an intuitive and numerically feasible approach to online validate the PE condition. The salient feature of the suggested methodology is that the rapid suppression of uncertainties in the controlled system can be achieved without using a large, high‐gain induced, learning rate in the adaptive laws. Extensive simulations are given to show the effectiveness and the improved response of the proposed schemes. Copyright © 2016 John Wiley & Sons, Ltd.     

Improving the performance of low-gain designs for bounded control of linear systems

Several solutions of the problem of stabilizing linear systems with bounded control rely on a one-parameter family of low-gain linear control laws u=K(ε)x. This paper presents an online scheduling of the parameter ensuring, in addition to closed-loop stability, the fastest possible transient between two extreme values of ε, chosen for stability and performance, respectively.     

An analytical study on optimizing the lookup performance of distributed hash table systems under churn

The phenomenon of system churn degrades the lookup performance of distributed hash table (DHT) systems greatly. To handle the churn, a number of approaches have been proposed to date. However, there is a lack of theoretical analysis to direct how to make design choices under different churn rates and how to configure their parameters optimally. In this paper, we analytically study three important aspects on optimizing DHT lookup performance under churn, i.e. lookup strategy, lookup parallelism and lookup key replication. Our objective is to build a theoretical basis for designers to make better design choices in the future. We first compare the performance of two representative lookup strategies—recursive routing and iterative routing—and explore the existence of better alternatives. Then we study the effectiveness of lookup parallelism in systems with different churn rates and show how to select the optimal degree of parallelism. Owing to the importance of key replication on lookup performance, we also analyze the reliability of the replicated key under two different replication policies, and show how to perform proper configuration. Besides the analytical study, our results are also validated by simulation, and Kad is taken as a case to show the meaningfulness of our analysis. Copyright © 2007 John Wiley & Sons, Ltd.     

Improving the tracking performance of mechanical systems by adaptive extended friction compensation

The paper discusses a tracking control system and shows with simulation and experimental results that extended friction models can be successfully incorporated in a computed-torque-like adaptive control scheme. The friction model used includes Coulomb, viscous, and periodic friction with sense of direction dependent parameters. To get small tracking errors, adaptation of the friction model parameters is necessary. The tracking performance is an order of magnitude better than with PD control. The robustness of the scheme for parameter inaccuracies is sufficient, owing to the adaptation, but the controller gains are limited due to stability problems caused by unmodeled dynamics.     

Adaptive dynamic CMAC neural control of nonlinear chaotic systems with L2 tracking performance

The advantage of using cerebellar model articulation control (CMAC) network has been well documented in many applications. However, the structure of a CMAC network which will influence the learning performance is difficult to select. This paper proposes a dynamic structure CMAC network (DSCN) which the network structure can grow or prune systematically and their parameters can be adjusted automatically. Then, an adaptive dynamic CMAC neural control (ADCNC) system which is composed of a computation controller and a robust compensator is proposed via second-order sliding-mode approach. The computation controller containing a DSCN identifier is the principal controller and the robust compensator is designed to achieve L₂ tracking performance with a desired attenuation level. Moreover, a proportional–integral (PI)-type adaptation learning algorithm is derived to speed up the convergence of the tracking error in the sense of Lyapunov function and Barbalat’s lemma, thus the system stability can be guaranteed. Finally, the proposed ADCNC system is applied to control a chaotic system. The simulation results are demonstrated that the proposed ADCNC scheme can achieve a favorable control performance even under the variations of system parameters and initial point.     

A unified approach to output synchronization of heterogeneous multi-agent systems via L2-gain design

In this paper, a unified design procedure is given for output synchronization of heterogeneous multi-agent systems (MAS) on communication graph topologies, using relative output measurements from neighbors. Three different control protocols, namely, full-state feedback, static output-feedback, and dynamic output-feedback, are designed for output synchronization. It is seen that a unified design procedure for heterogeneous MAS can be given by formulation and solution of a suitable local $\mathcal{L}{_2}$-gain design problem. Sufficient conditions are developed in terms of stabilizing the local agents'' dynamics, satisfying a certain small-gain criterion, and solving the output regulator equations. Local design procedures are presented for each agent to guarantee that these sufficient conditions are satisfied. The proposed control protocols require only one copy of the leader''s dynamics in the compensator, regardless of the dimensions of the outputs. This results in lower-dimensional compensators for systems with high-order outputs, compared to the $p$-copy internal model approach. All three proposed control protocols are verified using numerical simulations.     

Improving the performance and functionality of Mondrian open‐source OLAP systems

For a long time, the design of relational databases has focused on the optimization of atomic transactions (insert, select, update or delete). Currently, relational databases store tactical information of data warehouses, mainly for select‐like operations. However, the database paradigm has evolved, and nowadays on‐line analytical processing (OLAP) systems handle strategic information for further analysis. These systems enable fast, interactive and consistent information analysis of data warehouses, including shared calculations and allocations. OLAP and data warehouses jointly allow multidimensional data views, turning raw data into knowledge. OLAP allows ‘slice and dice’ navigation and a top‐down perspective of data hierarchies. In this paper, we describe our experience in the migration from a large relational database management system to an OLAP system on top of a relational layer (the data warehouse), and the resulting contributions in open‐source ROLAP optimization. Existing open‐source ROLAP technologies rely on summarized tables with materialized aggregate views to improve system performance (in terms of response time). The design and maintenance of those tables are cumbersome. Instead, we intensively exploit cache memory, where key data reside, yielding low response times. A cold start process brings summarized data from the relational database to cache memory, subsequently reducing the response time. We ensure concurrent access to the summarized data, as well as consistency when the relational database updates data. We also improve the OLAP functionality, by providing new features for automating the creation of calculated members. This makes it possible to define new measures on the fly using virtual dimensions, without re‐designing the multidimensional cube. We have chosen the XML/A de facto standard for service provision. Copyright © 2008 John Wiley & Sons, Ltd.