基于自适应蚁群算法的软硬件划分

为了更好地解决软硬件双路划分问题,提出一种自适应蚁群算法．基本思想是：对状态转移概率与信息素挥发因子,采取自适应调节策略．保证了算法前期蚁群的随机性较大,可以充分全局搜索;算法后期蚁群的随机性降低,以使算法在较短的时间内收敛．对不同节点的控制数据流图进行仿真实验,表明在同等条件下,相对于改进模拟退火、改进禁忌搜索、改进蚁群算法以及ＤＣＧ３Ａ 方法,所提出算法的命中率与收敛时间结果均更优．节点规模越大,优势尤其明显．     

Hardware/software interface codesign for embedded systems

Separate hardware- and software-only engineering approaches cannot meet the increasingly complex requirements of embedded systems. HW/SW interface codesign would enable the integration of components in heterogeneous multiprocessors. The authors analyze the evolution of this approach and define a long-term roadmap for future success.     

Hardware/software co-design for particle swarm optimization algorithm

This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve design flexibility and execution performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a Particle Updating Accelerator module via hardware implementation for updating velocity and position of particles and a Fitness Evaluation module implemented either on a soft-cored processor or Field Programmable Gate Array (FPGA) for evaluating the objective functions are respectively designed to work closely together to carry out the evolution process at different design stages. Thanks to the design flexibility, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To further improve the execution performance of the PSO, a hardware random number generator (RNG) is also designed in this paper in addition to a particle re-initialization scheme to promote exploration search during the optimization process. Experimental results have demonstrated that the proposed HW/SW co-design approach for PSO algorithms has good efficiency for obtaining high-quality solutions for embedded applications.     

System and application software for the Armstrong multiprocessor

The authors identify problems with present parallel processing systems, and present Armstrong, a hardware-software system that is designed to address some of the problems discussed. They briefly describe the Armstrong hardware and discuss, in depth, the operating system software, and performance of the system on a real application, namely, and computation of the 2-D discrete Fourier transform of an image     

Shared memory multiprocessor architectures for software IP routers

We propose new shared memory multiprocessor architectures and evaluate their performance for future Internet protocol (IP) routers based on symmetric multiprocessor (SMP) and cache coherent nonuniform memory access (CC-NUMA) paradigms. We also propose a benchmark application suite, RouterBench, which consists of four categories of applications representing key functions on the time-critical path of packet processing in routers. An execution driven simulation environment is created to evaluate SMP and CC-NUMA router architectures using this RouterBench. The execution driven simulation can produce accurate cycle-level execution time prediction and reveal the impact of various architectural parameters on the performance of routers. We port the FUNET trace and its routing table for use in our experiments. We find that the CC-NUMA architecture provides an excellent scalability for design of high-performance IP routers. Results also show that the CC-NUMA architecture can sustain good lookup performance, even at a high frequency of route updates.     

Software support for multiprocessor latency measurement andevaluation

Parallel computing scalability evaluates the extent to which parallel programs and architectures can effectively utilize increasing numbers of processors. In this paper, we compare a group of existing scalability metrics and evaluation models with an experimental metric which uses network latency to measure and evaluate the scalability of parallel programs and architectures. To provide insight into dynamic system performance, we have developed an integrated software environment prototype for measuring and evaluating multiprocessor scalability performance, called Scale-Graph. Scale-Graph uses a graphical instrumentation monitor to collect, measure and analyze latency-related data, and to display scalability performance based on various program execution patterns. The graphical software tool is X-Windows based and is currently implemented on standard workstations to analyze performance data of the KSR-1, a hierarchical ring-based shared-memory architecture     

Hardware/software trade-offs for bitmap graphics on the blit

The Blit is an experimental bitmap graphics terminal built for research into interactive computer graphics on the UNIX time-sharing system. The hardware is inexpensive and the graphics functions are implemented entirely in software. Nevertheless, the graphics performance of the Blit is comparable or superior to some displays with special-purpose graphics hardware. This paper explains the paradox by referring to some principles of design: the hardware and software should be designed together to complement each other; carefully designed software can outperform infelicitous hardware; and simplicity of design leads to efficiency of execution. These principles are illustrated by examples from the Blit hardware and software and comparisons with other systems.     

Hardware support for adaptive tessellation of Bézier surfaces based on local tests

Bézier representations have been widely employed as a standard way of designing complex scenes with very good quality results. These surfaces are usually tessellated, in the software application, into triangle models to be rendered. Then, the final image is generated in the graphics card so that its triangle rendering capabilities are exploited.In this work we present an adaptive tessellation algorithm and the corresponding architecture to be implemented in hardware. The objective of the proposal is to avoid the potential bottleneck associated with the transmission of complex triangular models from CPU to graphics cards. The algorithm we propose is based on a layer strip representation method and a new data management that permits generation and efficient storage of the tessellated mesh. The corresponding architecture has to be included as an additional unit at the input of the graphics card. As a consequence, the transmission requirements from CPU to graphics card are greatly reduced as the tessellation is performed in the graphics card. On the other hand, the adaptive strategy employed permits selection of the number of triangles of the final mesh as a trade off between computational requirements and quality of the final mesh. The efficient data management proposed, together with the low storage requirements of the architecture, makes it a good candidate for its hardware implementation and inclusion in future graphics cards.     

Online adaptive utilization control for real-time embedded multiprocessor systems

Many embedded systems have stringent real-time constraints. An effective technique for meeting real-time constraints is to keep the processor utilization on each node at or below the schedulable utilization bound, even though each task’s actual execution time may have large uncertainties and deviate a lot from its estimated value. Recently, researchers have proposed solutions based on Model Predictive Control (MPC) for the utilization control problem. Although these approaches can handle a limited range of execution time estimation errors, the system may suffer performance deterioration or even become unstable with large estimation errors. In this paper, we present two online adaptive optimal control techniques, one is based on Recursive Least Squares (RLS) based model identification plus Linear Quadratic (LQ) optimal controller; the other one is based on Adaptive Critic Design (ACD). Simulation experiments demonstrate both the LQ optimal controller and ACD-based controller have better performance than the MPC-based controller and the ACD-based controller has the smallest aggregate tracking errors.     

Hardware support for interprocess communication

The use of a special-purpose coprocessor for supporting message passing is proposed. An actual message-based operating system is partitioned into computation and communication parts, executing, respectively, on a host and a message coprocessor which interact through shared queues. Its performance is measured on a multiprocessor. Hardware support in the form of a special-purpose smart bus and smart shared memory is designed. The benefits of these components are demonstrated through analytical modeling using generalized timed Petri nets. The analysis shows good agreement with experimental results and indicates that substantial benefits may be obtained when the software is partitioned between host and the message coprocessor and when a small amount of special-purpose hardware is added     

基于免疫算法的嵌入式系统软硬件划分方法

软硬件划分是嵌入式系统协同设计的关键问题之一。提出了一种划分模型,并通过改进的免疫算法解决了在多约束条件下软硬件划分的优化问题。在该免疫算法中,引入了免疫算子,通过从以往经验中提取疫苗,在生成子代过程中注入疫苗,使划分算法得到了优化。实验表明该算法具有较快的收敛速度,并且在总体性能上优于传统遗传算法。     

Hardware/software cost analysis of interrupt processing strategies

A new study compares the architectural design and implementation costs of five strategies that let pipelined processors support precise interrupts. Hardware dominates the cost of all strategies except checkpoint repair, which, depending on the implementation, can incur either high software or hardware costs     

Hardware and software for intelligent robotic systems

A hardware and software methodology for the design of the three interactive levels of intelligent robotic systems is proposed. The organization level is modeled as an expert system, the coordination level as a loosely coupled parallel processing system and the execution level as a series of specific hardware components which execute specific tasks. Microprocessor-based configurations and discrete logic design techniques are utilized for the overall system hardware configuration. The proposed methodology, does not violate the system hierarchical structure. A case study demonstrates the feasibility of the approach.     

硬盘保护卡的软硬件设计

本文从软、硬件两方面阐述了目前流行的硬盘保护卡的设计原理,剖析了软件方面的关键技术,给出了最简单的硬件电路原理图。     

Hardware/software codesign and rapid prototyping of embeddedsystems

The complexity and the short time to market of embedded systems require the use of automated techniques during the specification, implementation, and testing phases of such systems. Due to the cost requirements and the timing constraints of such systems, application-specific hardware solutions are often needed, making the codesign of hardware and software a major topic for the design automation of embedded systems. This article describes tools for the analysis, synthesis, and rapid prototyping of distributed embedded real-time systems and presents a complete design flow from specification to implementation     

A design flow for supporting component-based software development in multiprocessor real-time systems

Component-based software development established as an effective technique to cope with the increasing complexity of modern computing systems. In the context of real-time systems, the M-BROE framework has been recently proposed to efficiently support component-based development of real-time applications on multiprocessor platforms in the presence of shared resources. The framework relies on a two-stage approach where software components are first partitioned upon a virtual multiprocessor platform and are later integrated upon the physical platform by means of component interfaces that abstract from the internal details of the applications. This work presents a complete design flow for the M-BROE framework. Starting from a model of software components, a first method is proposed to partition applications to virtual processors and perform a synthesis of multiple component interfaces. Then, a second method is proposed to support the integration of the components by allocating virtual processors to physical processors. Both methods take resource sharing into account. Experimental results are also presented to evaluate the proposed methodology.     

Hardware support for memory protection in sensor nodes

With reference to the typical hardware configuration of a sensor node, we present the architecture of a memory protection unit (MPU) designed as a low-complexity addition to the microcontroller. The MPU is aimed at supporting memory protection and the privileged execution mode. It is connected to the system buses, and is seen by the processor as a memory-mapped input/output device. The contents of the internal MPU registers specify the composition of the protection contexts of the running program in terms of access rights for the memory pages. The MPU generates a hardware interrupt to the processor when it detects a protection violation. The proposed MPU architecture is evaluated from a number of salient viewpoints, which include the distribution, review and revocation of access permissions, and the support for important memory protection paradigms, including hierarchical contexts and protection rings.