Yield analysis and process modeling of low cost, high throughputflip chip assembly based on no-flow underfill materials

As a concept to achieve low-cost, high-throughput flip chip on board (FCOB) assembly, a new process has been developed implementing next generation flip chip processing based no-flow fluxing underfill materials. The low-cost, high throughput flip chip process implements large area underfill printing, integrated chip placement and underfill flow and simultaneous solder interconnect reflow and underfill cure. The goals of this study are to demonstrate feasibility of no flow underfill materials and the high throughput flip chip process over a range of flip chip configurations, identify the critical process variables affecting yield, analyze the yield of the high throughput flip chip process, and determine the impact of no-flow underfill materials on key process elements. Reported in this work is the assembly of a series of test vehicles to assess process yield and process defects. The test vehicles are assembled by depositing a controlled mass of underfill material on the chip site, aligning chip to the substrate pads, and placing the chip inducing a compression type underfill flow. The assemblies are reflowed in a commercial reflow furnace in an air atmosphere to simultaneously form the solder interconnects and cure the underfill. A series of designed experiments identify the critical process variables including underfill mass, reflow profile, placement velocity, placement force, and underfill material system. Of particular interest is the fact that the no-flow underfill materials studied exhibit an affinity for unique reflow profiles to minimize process defects     

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials.     

Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials

The formation of underfill voids is an area of concern in the low cost, high throughput, or "no-flow" flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height, solder mask opening height, pad/solder mask opening separation, and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement, and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.     

Field reworkable underfill materials for flip chip on boardassemblies

Studies have shown that underfill encapsulation dramatically improves the solder joint fatigue reliability of flip chip on board (FCOB) assemblies. The lack of reworkability of the underfill after the product is in the field has limited the integration of FCOB into cost sensitive electronic products and the continued proliferation of the FCOB technology will depend on the development of reworkable underfill materials systems. This paper presents data that correlates reliability performance to mechanical properties for twelve field reworkable underfill materials from three different suppliers. Their respective properties, processing parameters, and reliability performances are compared to the qualified, commercially available high performance underfills. Techniques were developed to redress the printed wiring board (PWB) site to enhance the reworked FCOB assembly yield. In addition, reliability performance results and failure analysis observations were compared to the first time nonreworked assemblies     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

No-flow underfill flip chip assembly––an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.     

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.     

Near Void-Free Assembly Development of Flip Chip Using No-Flow Underfill

The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite of such challenges, a high yield, reliable assembly process (>99.99%) has been achieved using commercial no-flow underfill material with a high I/O, fine-pitch FCIP. This has been obtained using design of experiments with physical interpretation techniques. Statistical analysis determined what assembly conditions should be used in order to achieve robust interconnects without disrupting the FCIP interconnect structure. However, the resulting high yield process had the side effect of causing a large number of voids in the FCIP assemblies. Parametric studies were conducted to develop assembly process conditions that would minimize the number of voids in the FCIP induced by thermal effects. This work has resulted in a significant reduction in the number of underfill voids. This paper presents systematic studies into yield characterization, void formation characterization, and void reduction through the use of structured experimentation which was designed to improve assembly yield and to minimize the number of voids, respectively, in FCIP assemblies.     

Adhesion issues in flip-chip on organic modules

Flip chip attach on organic carriers is a novel electronic packaging assembly method which provides advantages of high input/output (I/O) counts, electrical performance and thermal dissipation. In this structure, the flip chip device is attached to organic laminate with predeposited eutectic solder. Mechanical coupling of the chip and the laminate is done via underfill encapsulant materials. As the chip size increases, the thermal mismatch between silicon and its organic carrier becomes greater. Adhesion becomes an important factor since the C4 joints fail quickly if delamination of the underfill from either chip or the solder mask interface occurs. Newly developed underfills have been studied to examine their properties, including interfacial adhesion strength, flow characteristics, void formation and cure kinetics. This paper will describe basic investigations into the properties of these underfills and also how these properties related to the overall development process. In addition, experiments were performed to determine the effects on adhesion degradation of flip chip assembly processes and materials such as IR reflow profile, flux quantity and residues. Surface treatment of both the chip and the laminate prior to encapsulation were studied to enhance underfill adhesion. Accelerated thermal cycling and highly accelerated stress testing (HAST) were conducted to compare various underfill properties and reliability responses     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

Assembly of lead-free bumped flip-chip with no-flow underfills

Lead-free solder reflow process has presented challenges to no-flow underfill material and assembly. The currently available no-flow underfill materials are mainly designed for eutectic Sn-Pb solders. This paper presents the assembly of lead-free bumped flip-chip with developed no-flow underfill materials. Epoxy resin/HMPA/metal AcAc/Flux G system is developed as no-flow underfills for Sn/Ag/Cu alloy bumped flip-chips. The solder wetting test is conducted to demonstrate the fluxing capability of the underfills for lead-free solders. A 100% solder joint yield has been achieved using Sn/Ag/Cu bumped flip-chips in a no-flow process. A scanning acoustic microscope is used to observe the underfill voiding. The out-gassing of HMPA at high curing temperatures causes severe voiding inside the package. A differential scanning calorimeter (DSC) used to study the curing degree of the underfill after reflow with or without post-cure. The post-curing profiles indicate that the out-gassing of HMPA would destroy the stoichiometric balance between the epoxy and hardener, and result in a need for high temperature post-cure. The material properties of the underfills are characterized and the influence of underfill out-gassing on the assembly and material properties is investigated. The impact of lead-free reflow on the material design and process conditions of no-flow underfill is discussed.     

Adhesion characterization of no-flow underfills used in flip chipassemblies and correlation with reliability

Adhesion is one of the key properties of underfills used in flip chip assemblies. This paper characterizes the adhesion strengths of no-flow underfill materials to various die passivations using the shear test techniques. A novel shear test vehicle with planner underfill layers between the die and substrate is presented. The adhesion strengths and failure modes of the no-flow underfill materials during shear testing correlate well with their thermal shock reliability test results. Underfill adhesion related failures such as delamination and crack are investigated and correlated between flip chip assemblies and shear test vehicle assemblies without solder joint interconnects     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

有机印制板上倒装芯片的可靠性研究

对一种有机印制板上倒装芯片（Ｆｌｉｐｃｈｉｐ）进行温度循环试验,测出其失效分布曲线,然后通过扫描声显微镜、红外显微镜和剖面等失效分析手段,发现失效模式主要是合金焊点中的断裂以及下部填充料（Ｕｎｄｅｒｆｉｌ）中的损伤如分层（Ｄｅｌａｍｉｎａｔｉｏｎ）和内部裂缝（Ｃｒａｃｋ）。详细地阐述了倒装芯片中的下部填充料损伤在温度循环试验条件下的产生、发展及它们对合金焊点可靠性的影响。     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Guidelines to select underfills for flip chip on board assemblies and compliant interposers for chip scale package assemblies

The effect of thermomechanical properties of underfill and compliant interposer materials, such as coefficient of thermal expansion (CTE) and stiffness (Young's modulus) on reliability of flip chip on board (FCOB) and chip scale packages (CSPs) under thermal cycling stresses is investigated in this study. Quasi-three-dimensional viscoplastic stress analysis using finite element modeling (FEM) is combined with an energy partitioning (EP) model for creep-fatigue damage accumulation to predict the fatigue durability for a given thermal cycle. Parametric FEM simulations are performed for five different CTEs and five different stiffnesses of the underfill and compliant interposer materials. The creep work dissipation due to thermal cycling is estimated with quasi 3-D model, while 3-D model is used to estimate the hydrostatic stresses. To minimize the computational effort, the 3-D analysis is conducted only for the extreme values of the two parameters (CTE and stiffness) and the results are interpolated for intermediate values. The results show that the stiffness of the underfill material as well as the CTE play important role in influencing the fatigue life of FCOB assemblies. The fatigue durability increases as underfill stiffness and CTE increase. In the case of compliant interposers, the reverse is true and durability increases as interposer stiffness decreases. Furthermore, the interposer CTE affects the fatigue durability more significantly than underfill CTE, with durability increasing as CTE decreases. The eventual goal is to define the optimum design parameters of the FCOB underfill and CSP interposer, in order to maximize the fatigue endurance of the solder joints under cyclic thermal loading environments.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

A new defect in which a chip "floats" over the board surface after chip placement is appearing in the low-cost, high-throughput flip chip on board (FCOB) assembly that is based on no-flow underfill. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." A process model has been developed that will allow an understanding of the underlying physics of the floating phenomena and identification of process variables so that this process defect can be eliminated. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the theoretical model's predictions.