基于LM5117降压型开关电源的设计

本系统以LM5117芯片和CSD18532KCS MOS管为核心器件,采用Buck降压电路,通过LM5117芯片的PWM波来控制CSD18532KCS MOS管,调整PWM波的占空比,得到稳压输出.通过测试,在输入直流电压16V的情况下,额定输出直流电压为5V,输出电流最大值为3A;输出纹波小于25mV,负载调整率小于2.5%,电压调整率小于0.22%,效率可以达到85.2%.     

A New Approach to Reducing Output Ripple in Switched-Capacitor-Based Step-Down DC–DC Converters

Rapidly dropping power supply voltages and tight voltage regulation requirements for integrated circuits challenges power supply designers. A novel interleaved discharging (ID) approach is presented to reduce the output ripple in step-down switched-capacitor (SC) dc-dc converters. Simulation and experimental results of a four-stage SC dc-dc converter show that the ID approach can reduce the output ripple by a factor of three. The proposed approach also improves the converter efficiency by 7%. The ID method provides flexibility in the design optimization of step-down SC dc-dc converters     

DC-DC变换器的大信号建模及鲁棒控制方法

本文从工程实践的要求出发,将建模和控制器的设计紧密结合,提出了一种新型DC-DC变换器大信号建模方法,基于这一模型,将线性时变不确定系统的鲁棒控制方法应用于DC-DC变换器的控制器设计.本文所提出的建模和控制器设计方法适用于全部四种基本PWM型DC-DC变换器.计算机仿真和实验证明,本文设计的控制器对输入电源电压扰动和线性负载电阻扰动具有良好的鲁棒性,且实现方案简单易行.     

An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control

Integrated switching power supplies with multimode control are gaining popularity in state-of-the-art portable applications like cellular phones, personal digital assistants (PDAs), etc., because of their ability to adapt to various loading conditions and therefore achieve high efficiency over a wide load-current range, which is critical for extended battery life. Constant-frequency, pulsewidth modulated (PWM) switching converters, for instance, have poor light-load efficiencies because of higher switching losses while pulse-frequency modulation (PFM) control in discontinuous-conduction mode (DCM) is more efficient at light loads because the switching frequency and associated switching losses are scaled down with load current. This paper presents the design and integrated circuit prototype results of an 83% power efficient 0.5-V 50-mA CMOS PFM buck (step-down) dc-dc converter with a novel adaptive on-time scheme that generates a 27-mV output ripple voltage from a 1.4- to 4.2-V input supply (battery-compatible range). The output ripple voltage variation and steady-state accuracy of the proposed supply was 5 mV (22-27 mV) and 0.6% whereas its constant on-time counterpart was 45 mV (10-55 mV) and 3.6%, respectively. The proposed control scheme provides an accurate power supply while achieving 2%-10% higher power efficiency than conventional fixed on-time schemes with little circuit complexity added, which is critical during light-loading conditions, where quiescent current plays a pivotal role in determining efficiency and battery-life performance     

Output ripple analysis of switching DC-DC converters

State space averaging methods are used to derive time-invariant models that bound the envelope of trajectories of pulsewidth modulated (PWM) dc-dc converters. The results are compared to conventional averaging methods used in power electronics, and it is shown that, at times, designing a dc-dc converter based on the averaged output of a converter can be ineffective because peak output values sometimes significantly deviate from the averaged output. This paper attempts to quantify this deviation by using both small-signal transfer functions and nonlinear models to model the maximum and minimum values of outputs of PWM converters. Issues in simulation and control loop design are also mentioned.     

High-power CSI-fed induction motor drive with optimal power distribution based control

In this article, a current source inverter (CSI) fed induction motor drive with an optimal power distribution control is proposed for high-power applications. The CSI-fed drive is configured with a six-step CSI along with a pulsewidth modulated voltage source inverter (PWM–VSI) and capacitors. Due to the PWM–VSI and the capacitor, sinusoidal motor currents and voltages with high quality as well as natural commutation of the six-step CSI can be obtained. Since this CSI-fed drive can deliver required output power through both the six-step CSI and PWM–VSI, this article shows that the kVA ratings of both the inverters can be reduced by proper real power distribution. The optimal power distribution under load requirements, based on power flow modelling of the CSI-fed drive, is proposed to not only minimise the PWM–VSI rating but also reduce the six-step CSI rating. The dc-link current control of the six-step CSI is developed to realise the optimal power distribution. Furthermore, a vector controlled drive for high-power induction motors is proposed based on the optimal power distribution. Experimental results verify the high-power CSI-fed drive with the optimal power distribution control.     

A novel self-oscillating, boost-derived DC-DC converter with load regulation

This paper proposes a novel self-oscillating, boost-derived (SOBD) dc-dc converter with load regulation. This proposed topology utilizes saturable cores (SCs) to offer self-oscillating and output regulation capabilities. Conventionally, the self-oscillating dc transformer (SODT) type of scheme can be implemented in a very cost-effective manner. The ideal dc transformer provides both input and output currents as pure, ripple-free dc quantities. However, the structure of an SODT-type converter will not provide regulation, and its oscillating frequency will change in accordance with the load. The proposed converter with SCs will allow output-voltage regulation to be accomplished by varying only the control current between the transformers, as occurs in a pulse-width modulation (PWM) converter. A control network that combines PWM schemes with a regenerative function is used for this converter. The optimum duty cycle is implemented to achieve low levels of input- and output-current ripples, which are characteristic of an ideal dc transformer. The oscillating frequency will spontaneously be kept near-constant, regardless of the load, without adding any auxiliary or compensation circuits. The typical voltage waveforms of the transistors are found to be close to quasisquare. The switching surges are well suppressed, and the voltage stress of the component is well clamped. The turn-on/turn-off of the switch is zero-voltage switching (ZVS), and its resonant transition can occur over a wide range of load current levels. A prototype circuit of an SOBD converter shows 86% efficiency at 48-V input, with 12-V, 100-W output, and presents an operating frequency of 100 kHz.     

An improved topology of inductor-switching DC-DC converter

An improved version of an inductor-switching fast-response dc-dc converter is presented that will provide the requirements and features of the new generation of microprocessor and digital systems. Lower output voltage, higher output current, and smaller output voltage ripple requirements have greatly increased the difficulty of the power supply design. To further increase the problem, power-saving "stop-clock" modes of the microprocessor has demanded faster and more stable transient response from the dc-dc converter. A novel method of inductor switching is applied to a dc-dc converter, and it provides the prominent features of current amplification and absorption during the heavy burden of load transients. The design and simulation of the concept is verified by experiment with a 12-V input and 3.3-V/30-A output converter.     

Digital Predictive Feed-Forward Controller for a DC–DC Converter in Plasma Display Panel

This paper describes a new digital control method to enhance the dynamic performance of a dc-dc converter used in plasma display panel (PDP). A simple digital PID compensator with duty ratio feed-forward control is proposed to minimize the output voltage variation while the load current is continuously changing. The duty ratio feed-forward is calculated using noise-free load current information which is predicted by the available video data of the PDP. No separate current sensing circuit is required. A small signal z-domain feed-forward model is derived for the performance analysis and controller design. The proposed control method is experimentally verified on an asymmetrical half bridge dc-dc converter which supplies power to a 42 in PDP.     

Uniform Voltage Distribution Control for Series Connected DC–DC Converters

This paper investigates applications of current-mode, shared-bus commercial-off-the-shelf (COTS) dc-dc converters to power system architectures configured as parallel-input, series-output (PISO) and series-input, parallel-output (SIPO). By employing a PISO (or SIPO) architecture, current-mode COTS converters can transform their system input voltage to higher (or lower) system output voltage, provide ease and flexibility of power expansion, and preserve system efficiencies equal to those of standalone converters. Nonuniform output (or input) voltages still exist within a PISO (or SIPO) power system using identical converters when the system lacks proper distribution control of the series connected output (or input) voltages-and thus, system reliability suffers from thermal overstress to the converters that contribute a greater portion of the output power. Through unified approaches of voltage distribution control for the PISO and SIPO architectures, a series-connected converter power system attains robust stability and reliability. Two effective approaches to uniform voltage distribution control-the central-limit and maximum-limit voltage distribution-will be discussed. Both computer simulation and experimental prototypes validate both of the uniform voltage distribution power converter architectures.     

An Integrated Switching DC–DC Converter With Dual-Mode Pulse-Train/PWM Control

This brief presents an integrated switching converter with a dual-mode control scheme. A pulse-train (PT) control employing a combination of four pulse control patterns is proposed to achieve optimal regulation performance under various operation scenarios. Meanwhile, a high-frequency pulsewidth modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling in steady state. The converter was fabricated with a 0.35- $muhbox{m}$ digital CMOS n-well process. The entire die area, including the on-chip pads and power devices, is 1.31 $hbox{mm}^{2}$ . Experimental results show that, in the steady state, the output voltage is well regulated at 1.5 V with $pm$12.5-mV ripples in the PWM mode. The measured maximum efficiency is 91%, and the efficiency stays above 70% within the entire 500-mW power range. In transient measurements, with a 100% load step change from 50 to 100 mA, the output voltage of the converter settles within 345 ns due to the fast response of the PT control, with a maximum voltage variation of 164 mV. The converter functions well when the input supply voltage frequently varies between 2.2 and 3.3 V, with a line regulation of 29.1 mV/V.      

Voltage loop of boost PWM DC-DC converters with peak current-mode control

A new transfer function from control voltage to duty cycle, the closed-current loop, which captures the natural sampling effect is used to design a controller for the voltage-loop of a pulsewidth modulated (PWM) dc-dc converter operating in continuous-conduction mode (CCM) with peak current-mode control (PCM). This paper derives the voltage loop gain and the closed-loop transfer function from reference voltage to output voltage. The closed-loop transfer function from the input voltage to the output voltage, or the closed-loop audio-susceptibility is derived. The closed-loop transfer function from output current to output voltage, or the closed loop output impedance is also derived. The derivation is performed using an averaged small-signal model of the example boost converter for CCM. Experimental verification is presented. The theoretical and experimental results were in good agreement, confirming the validity of the transfer functions derived.     

一种同步整流DC-DC转换器PWM控制电路设计

设计了一种改进的PWM控制电路,将电流采样电路和PWM比较器归结为一个PWM电流比较器,减少了电路规模。将误差放大器输出与锯齿波斜坡补偿信号叠加,产生叠加输出电流,并通过PWM电流比较器输出一个占空比信号,以控制功率管的通断。电压信号转换为电流信号,从而使控制回路反应速度更快。将PWM控制电路应用于一款BUCK型DC-DC同步整流开关电源稳压器中。HSPICE仿真表明,稳压器输出纹波电压为±4mV,输出电压精度为±1%。     

A fully integrated on-chip DC-DC conversion and power management system

It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. Most on-chip dc-dc conversion systems have relied on buck converters with off-chip LC filters. In this paper, we describe the development of a software controllable, fully integrated on-chip dc-dc downconversion system that combines switched-capacitor voltage dividers and linear regulators to efficiently regulate from 2.5 V down to about 0.65 V. The use of switched-capacitor supplies offers better efficiencies than what is achievable with linear regulators alone.     

Design and analysis of switched-coupled-inductor switched-capacitor step-up DC-DC converter

The study presents a high-gain closed-loop configuration of switched-coupled-inductor switched-capacitor (SCISC) converter via integrating with a pulse-width-modulation-based (PWM) controller for the goal of step-up DC-DC conversion/regulation. The SCISC power part consists of switched-coupled-inductor booster (SCI booster) and switched-capacitor tripler (SC tripler), and the step-up voltage gain is performed by using appropriate duty ratio D of PWM and turn ratio n of coupled inductor. Although increasing n or raising D makes a higher gain, it often results in the larger weight/volume or magnetic bias/saturation of coupled inductor. Here, the SC tripler can provide for an extra gain to ease these stresses of the coupled inductor. Further, this controller is engaged not merely in doing topological operation and timing, but in enhancing output regulation and/or output robustness (against source/loading variation). The related studies are demonstrated as follows: modelling, steady-state response, voltage conversion ratio value, power efficiency, capacitance/inductance selection, system stability and control design. At the end, the simulation results are obtained to check the design/analysis validity, and the experimental results are verified on the prototype of SCISC to display the effect of the proposed scheme.     

Discrete sliding-mode control of a PWM inverter for sinusoidaloutput waveform synthesis with optimal sliding curve

This paper presents a discrete sliding-mode control scheme with feedforward compensation for the closed-loop regulation of the pulse-width modulated (PWM) inverter used in an uninterruptible power supply (UPS). The proposed feedforward controller can effectively improve the tracking performance of the PWM inverter. In designing the sliding-mode controller, we have taken load disturbance into consideration to enhance the robustness of the PWM inverter. Moreover, the upper bound of the load disturbance under which the sliding condition can be maintained has also been derived. The sliding curve of the sliding-mode controller is designed such that the behavior of the controlled PWM inverter is optimal subject to the selected cost function. Due to the coordinate transformation proposed in this paper, only the output voltage needs to be measured as feedback for the purpose of closed-loop regulation. Simulation and experimental results are given to show the effectiveness of the proposed control scheme     

Dynamic and steady state analysis of a three phase buck rectifier

Current source rectifiers among other alternatives, offer several advantages over line commutated rectifiers. Advantages include displacement power factor control and reduced line current harmonic distortion. This paper analyzes the current source rectifier (CSR) in transient and steady state, the models are developed in a synchronous reference frame. The load behavior is characterized for two load conditions, resistive load or, in general, increasing current for increasing voltage, and constant output power, decreasing output current for increasing voltage. Constant power operation can occur for a converter system supplying a pulse width modulation (PWM) inverter with high dynamics. Several static converter characteristics such as power factor, real and reactive power are analyzed for both types of load. Transient characteristics are analyzed for both types of load by exact small-signal model with full set of equations     

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation

A dual-branch 1.8 V to 3.3 V regulated switched-capacitor voltage doubler with an embedded low dropout regulator is presented. For the power stage, the power switches are individually controlled by their phase signals using a phase-delayed gate drive scheme, and are turned on and off in proper sequence to eliminate both short-circuit and reversion currents during phase transitions. For the regulator, the two branches operate in an interleaving fashion to achieve continuous output regulation with small output ripple voltage. Dual-loop feedback capacitor multiplier is adopted for loop compensation and a P-switch super source follower with high current sinking capability is inserted to drive switching capacitive load, and push the pole at the gate of the output power transistor to high frequency for better stability. The regulated doubler has been fabricated in a 0.35 $mu{hbox {m}}$ CMOS process. It operates at a switching frequency of 500 kHz with an output capacitor of 2 $muhbox{F}$ , and the maximum output voltage ripple is only 10 mV for a load current that ranges from 10 mA to 180 mA. The load regulation is 0.0043%/mA, and the load transient is 7.5 $mu{hbox {s}}$ for a load change of 160 mA to 10 mA, and 25 $mu{hbox {s}}$ for a load change of 10 mA to 160 mA.      

Phase control for resonant DC-DC converter with class-DE inverter and class-E rectifier

In this paper, a phase control scheme for Class-DE-E dc-dc converter is proposed and its performance is clarified. The proposed circuit is composed of phase-controlled Class-DE inverter and Class-E rectifier. The proposed circuit achieves the fixed frequency control without frequency harmonics lower than the switching frequency. Moreover, it is possible to achieve the continuous control in a wide range of the line and load variations. The output voltage decreases in proportion to the increase of the phase shift. The proposed converter keeps the advantages of Class-DE-E dc-dc converter, namely, a high power conversion efficiency under a high-frequency operation and low switch-voltage stress. Especially, high power conversion efficiency can be kept for narrow range control. We present numerical calculations for the design and the numerical analyses to clarify the characteristics of the proposed control. By carrying out circuit experiments, we show a quantitative similarity between the numerical predictions and the experimental results. In our experiments, the measured efficiency is over 84% with 2.5 W output power for 1.0-MHz operating frequency at the nominal operation. Moreover, the output voltage is regulated from 100% to 39%, keeping over 57% power conversion efficiency by using the proposed control scheme.     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。