EDMA数据传输方式在基于DSP的视频信号处理系统中的应用

视频信号传输是视频信号处理系统的关键技术,文章介绍利用EDMA数据传输方式、在基于TI公司的数字信号处理器(DSP)TMS320C6713芯片的视频信号处理系统中实现视频数据信号高速传输的一种方案。介绍了方案中的DSP外部储存器接口与FIFO存储器的硬件接口设计,并着重描述了基于EDMA数据传输方式的实现方法和软件设计流程。利用EDMA在CPU后台高效地实现存储空间的数据搬移,并在EDMA中断服务程序中对视频数据信号进行处理,DSP的中央处理单元就能够专注于信号处理和系统功能控制,从而满足视频信号处理系统的高速实时性要求。     

3GPP网络中的IPv6地址分配

本文首先介绍了IPv6在3GPP(3rd generation partnership project)网络中的应用,然后对3GPP和IETF提出的3GPP网络中的IPv6地址分配方案进行了比较,最后提出了一种新的3GPP网络中的IPv6地址分配方案.     

Code Optimization Techniques in Embedded DSP Microprocessors

We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventional code generation methods typically result in inefficient code. In this paper we formulate and solve some optimization problems that arise in code generation for processors with irregular datapaths. In addition to instruction scheduling and register allocation, we also formulate the accumulator spilling and mode selection problems that arise in DSP microprocessors. We present optimal and heuristic algorithms that determine an instruction schedule simultaneously optimizing accumulator spilling and mode selection. Experimental results are presented.     

CMTS中PCI地址到Lbus地址映射的实现

结合CMTS中PCI地址到Lbus地址映射的实例,介绍了其中的映射原理,阐述了其中以有限的PCI地址访问庞大Lbus内存的原理,并给出在VxWorks中生成访问Lbus内存所需PCI地址的源代码.     

接入网IPv6地址的规划与分配方法

讨论了接入网中IPv6地址的规划原则,以及SLAAC,DHCP和PPP3种IPv6地址的分配方法及其优缺点。     

Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures

We address the problem of code generation for DSP systems on a chip. In such systems, the amount of silicon devoted to program ROM is limited, so in addition to meeting various high-performance constraints, the application software must be sufficiently dense. Unfortunately, existing compiler technology is unable to generate high-quality code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. Thus, designers often resort to programming application software in assembly, which is a very tedious and time-consuming task. In this paper, we focus on providing compiler support for a group of specialized architectural features that exist in many DSPs, namely indirect addressing modes with auto-increment/decrement arithmetic. In these DSPs, an indexed addressing mode is generally not available, so automatic variables must be accessed by allocating address registers and performing address arithmetic. Subsuming address arithmetic into auto-increment /decrement arithmetic improves both the performance and size of the generated code. Our objective is to provide a method for comprehensively analyzing the performance benefits and hardware cost due to an auto-increment /decrement feature that varies from-l to +l, and allowing access to k address registers in an address generator. We provide this method via a parameterizable optimization algorithm that operates on a procedure-wise basis. Thus, the optimization techniques in a compiler can be used not only to generate efficient or compact code, but also to help the designer of a custom DSP architecture make decisions on address arithmetic features.     

DSP在软件无线电接收机中的应用

数字信号处理器（DSP）是鉴于数字滤波和快速傅立叶变换的数字信号处理技术。本文指出在软件无线电（Software Radio)接收机中，DSP技术是其核心技术之一。在接收机中，模拟信号进行数字化后的处理任务全由DSP软件承担，主要完成各种数据流相对较低的基带信号的处理。以TI公司TMS320C5410为例，介绍了其主要结构和特征，并给出了以此为核心的软件无线电接收机的系统框图。     

数据传输系统中CRC校验的DSP算法实现

循环冗余校验码是一种重要的循环码,编码和解码方法简单,容易实现,检错能力强,误判概率几乎为零,是一种效率极高的差错控制方法,可以满足通信系统可靠传送信息的要求,在测控及数据通信中得到了非常广泛的应用。详细介绍了循环冗余校验的编解码原理,分析了用DSP实现CRC的合理性,最后给出了根据校验原理实现的设计思想及流程图,具有一定的实用价值。     

基于EDA技术的高速FIFO设计

利用Lattice公司的在系统可编程逻辑器件ispLSI6192芯片构造4个双向、独立的128×9位F IFO高速数据存储栈区(FIFO),并对芯片可编程逻辑编程建立快速地址加1计数器以及FIFO控制逻辑,控制逻辑分别对4个FIFO栈区进行读/写控制;实现将系统的高速数据栈区及其控制逻辑功能在同一个芯片上实现,从而提高计算机数据通信的速度、效率以及提高系统的集成度和降低系统的故障率。     

基于DSP的实时数字滤波器设计

抗混滤波和频率细化（ZOOM）一直是数据采集和动态信号分析系统的两个关键问题和难点所在，本文介绍了采用基于数字信号处理器（DSP）的实时数字滤波技术实现这两种功能的原理和设计方法。结合自行研制的DTAS多通道动态测试分析系统，给出了这种设计的性能、特点及其应用实例。     

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such faults are the primary target of this study because they are hard-to-detect faults. These faults are caused by some particular defects which may appear in the parallel transistor network of the logic gates in the address decoders. With this study, we show that the test conditions required for ADOFs testing (sensitization and observation) are also useful for resistive-ADOFs detection, but more stringent timing requirements are needed. In the last part of the paper, we propose a study on the conditions to detect ADOFs with March tests. Moreover, we propose new March elements, which are effective for ADOF testing, and which can be added to existing March tests. *This work has been partially funded by the French government under the framework of the MEDEA+ A503 “ASSOCIATE” European program.     

LS-DSP地址产生器生成算法与逻辑实现

由于传统的内嵌地址产生器不能有效地支持数字信号处理应用的需要,在开发面向航天应用的高速信号处理器LS-DSP时,设计支持数字信号处理应用的地址产生器成为LS-DSP开发中的重要环节。本文通过研究常用的数字信号处理计算的数据地址运算特点,提出了LS-DSP地址产生器的生成算法。在根据该算法逻辑实现LS-DSP地址产生器时,为了减小地址产生器面积,针对循环类地址计算又提出了一种快速的动态START、END产生方法。实验结果表明,LS-DSP使用本文的地址产生器比采用传统的地址产生器可有效的提高数字信号处理运算的速度。     

基于以太网接口的DSP阵列通信系统设计

设计一种基于以太网技术的数字信号处理器(DSP)阵列系统,采用以太网交换芯片作为交换中枢,每个DSP有独立的MAC地址和IP地址,通过以太网交换芯片交互数据。硬件架构可根据需要随意扩展DSP的个数,DSP软件实现了链路检测方法,保证了通信的可靠性。     

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.     

基于中频存储和并行DSP的短波跳频侦察

介绍了采用中频信号存储和DSP并行处理技术的试验平台和基于该试验平台的短波跳频信号侦察方法,不但能够实现常规定频信号的搜索截获和分析测量,同时可对跳频、突发等短持续信号截获和识别。能快速截获50跳/s的跳频信号并获取其完备的频率集,测频精度优于50Hz。     

EPP模式下计算机并口与DSP的高速数据通信

介绍通过计算机增强型并口EPP协议和CPLD实现DSP与计算机并口双向高速数据通信,并详细分析了计算机增强型并口的工作方式,给出了具体的实现方案。该设计实现了计算机和DSP之间的高速数据交换,已经应用到某实时图像处理系统的图像数据传输模块中,并具有一定的通用性,可以应用到其他的科研项目中。     

单片机与DSP实验教学比对

在单片机和DSP实验教学中,有不少学生对单片机容易上手和理解,但就DSP来说就比较困难。本文从存储器结构等几个方面比对了MCS-51系列单片机和C54XDSP的异同,能够达到辅助教学的作用。     

加快内部地址变换的方法分析

分析了造成虚拟存储器速度降低的主要原因，介绍了加快查表速度的方法以及他们的优缺点。     

基于DSP的防尾随控制方法的实现

针对当今社会所要求的高安全性与防尾随控制技术的防范效果差的矛盾,介绍了一种基于DSP的门禁管理系统中防尾随控制方法的实现,提出了运用红外传感器与体重检测装置相配合并结合门禁射频卡进行防尾随控制,通过与传统方法进行比较,新方法控制效果更好,使门禁系统的安全性得到了更好的保证。     

数据采集系统中的DSP控制回路

在某些信号采集系统中,传感器的工作电压随着环境的变化而变化,这时高速的数据处理能力以及高精度的反馈控制能力就显得至关重要。介绍由TMS320VC5416和MAX5633所架构的生物信号传感器控制系统,给出高精度多通道D/A在数据采集系统中的应用方法,着重讨论TMS320VC5416与MAX5633的一种串行接口连接方法以及相关的软件实现方法。该系统能成功地解决工作电压变化所带来的问题,对数据采集系统的设计具有指导作用。