小区切换中随机接入过程的研究与验证

介绍了TD-LTE(时分-长期演进)系统所规范的小区切换过程,并重点研究了切换执行过程中的随机接入过程。结合TD-LTE协议一致性测试的特点和实际开发经验,通过执行无线资源管理异频切换测试例,对测试仿真图进行了分析,最后从仿真数据可以看到终端按源小区的前导配置向目标小区发起随机接入,有效验证了切换中的随机接入过程的协议一致性。     

系统网络端MAC层测试研究

协议一致性测试方式的选择对MAC协议实现过程是非常重要的,在设计TD-LTE(时分-长期演进)MAC层协议实现的基础上运用了一种SDL(规范描述语言)+TTCN(树表结合表示法)的测试方式对其随机接入过程多种情况进行测试,最后用ARM芯片集成项目代码对测试的结果进行了正确验证。     

GPON的MAC协议设计

参照ITU T建议草案:吉比特无源光网络传输汇聚层规范(G.GPON.gtc),提出了一种支持分组业务接入的媒质接入控制(MAC)协议.通过仿真建模对该协议的性能进行了分析.     

基于PWLAN GPF的QoS性能分析与仿真

基于IEEE802.11协议中PCF/DCF技术,在无线局域网(WLAN)中,介绍了GPF的系统结构和数据帧格式等。分别对基于IEEE802.11b媒体接入控制(MAC)协议、基于IEEE802.11e媒体接入控制(MAC)协议以及基于业务划分Qos的GPF仿真的时间参数和接入原则等进行了说明。在PWLAN的3种测试环境下,对802.11b、802.11e、GPF协议的整体性能进行了仿真,并对其结果进行了分析。     

分布式无线网络MAC层协议的研究

本文介绍了几种最新的信道接入协议,并且重点介绍了实地捕获多址接入协议(FAMA,Floor Acquisition Multiple Access)的信道接入过程,同时还通过仿真比较了FAMA-NCS、FAMA-NCS train和IEEE 802.11 MAC协议在不同网络模型下的性能,给出了仿真结果。由结果可知,在带有隐藏终端的分布式无线网络中FAMA协议是较好的选择。     

一种基于ALOHA协议特点的仿真计算方法

在信道资源珍贵的卫星通信系统中,多址通信技术可以共享信道资源,实现信道资源的高效利用。ALOHA协议是卫星通信系统中常用的多址接入技术,一直以来是该领域的研究热点。文章分析比较不同ALOHA协议特点,设计相应仿真计算模型,并结合具体多址接入应用场景进行系统参数仿真计算。通过将计算结果与相应ALOHA协议的理论值进行比较,文章验证了仿真计算模型的准确性,为系统应用提供数据支撑。     

高速局域网的简化CRMA协议性能分析

对现有的周期预留多址接入(CRMA)协议进行了简化和改进，提出了简化的CRMA协议(S-CRMA)。S-CRMA协议对时隙结构进行了重新定义，取消了原有协议的REJECT、CONFIRM等命令，通过自适应地改变预留时隙的间隔，实现了网络在接入时延和接入速率方面的公平性。通过仿真数据和曲线，说明了基于S-CRMA协议的网络在平衡突发业务和非平衡突发业务两种条件下，均保证了各个本地节点的公平接入。     

NB-IoT随机接入过程的研究与实现”

随机接入过程作为实现UE和网络端建立连接的重要过程,在NB-IoT系统中,它在LTE系统的基础上进行了相应的简化和修改。通过LTE-A系统和NB-IoT系统协议入手,对目前仅支持的基于竞争模式的随机接入过程进行了深入的分析和阐述,同时,也详细地分析NB-IoT中新增的Suspend-Resume过程,并具体介绍了随机接入过程的流程设计和实现。在SDL和TTCN协仿真平台上搭建了SDL功能块图,并生成了随机接入过程的MSC仿真图,验证了流程设计的正确性。     

TD-LTE多模终端异系统重选过程研究与实现

首先对TD-LTE多模终端的异系统重选过程进行了研究。在此基础上,对几个重选场景进行了协议栈的流程设计与实现,并通过规范和描述语言(SDL)/数表结合仿真法(TTCN)进行了仿真测试产生了MSC图,验证了信令流程的正确性。     

模拟集成电路的特点及设计平台

讨论了常规和射频模拟集成电路(IC)设计和工艺的特点，介绍了模拟集成电路设计平台，着重论述了电子设计自动化的软件工具、硬件平台，以及设计与工艺接口的设计数据库。详细介绍了模拟IC及RFIC的设计流程和工艺设计包。     

A modular approach to the communication protocol and standard for multimedia information: A review

The paper focuses on a modular approach to design of a communication protocol and an MPEG-like standard for multimedia information processing. Generally, the following basic problems can be considered: (i) selection, (ii) composition, and (iii) combinatorial evolution and forecasting. Here, the composition problem is examined. The ZigBee Protocol for wireless sensor networks is studied as an example for the modular design. A generalized MPEG-like standard is considered as a representative example as well. Morphological (modular) system design is used for composition of the elements (components) of the protocol/standard. The solving process is based on Hierarchical Morphological Multicriteria Design (HMMD): (i) multicriteria selection of alternatives for system components, (ii) synthesis of the selected alternatives into a resultant combination. Numerical examples illustrate the design process.     

An optimization design method for chemically amplified resistprocess control

A novel optimization method called chemically-amplified resist process optimization design (CARPOD) applicable to the chemically amplified resist (CAR) process development is described. The method finds the optimal process conditions and the design center (maximum process tolerance space) of a CAR process with minimum experimental runs. First a modified response surface method is used to form the numerical response surface of a CAR, and its most sensitive point, which is the minimum requirement of X-ray dose, is located as an optimal process condition by an optimization method called POSM under the constraint of the contrast of the photoresist. Second, the design center is found to maximize the process tolerance space around the optimal process condition. Third, verifications are made on the optimal design as well as the design center. The process optimization of AZ PF-514 has been used as an example to show that the CARPOD method can identify the optimal process condition as well as the maximum tolerable parameter space with minimum experimental runs     

Automated performance‐based design technique for an efficient LTE PDSCH implementation using SDSoC tool

System on a chip (SoC) creates massive design challenges for SoC‐based designers. The design challenges start from functional, architectural verification complexity and finally meeting performance constraints. In addition, heterogeneity of components and tools introduces long design cycles. The Software‐Defined System‐on‐Chip (SDSoC) developed by Xilinx is used to create custom SoC on a heterogeneous FPGA‐CPU platform. The SDSoC tool provides fast, flexible, and short design cycle to develop heterogeneous FPGA‐CPU platform. The objective of this paper is to introduce a new automated design technique to build a SoC on a heterogeneous FPGA‐CPU platform that meets design requirements using SDSoC tool. In this paper, the typical SDSoC design flow is introduced. In addition, a new automated SDSoC design technique is developed to design SoC on a heterogeneous FPGA‐CPU platform on the basis of performance metrics such as area, power, and latency. Design of physical downlink shared channel (PDSCH) in long‐term evolution (LTE) is presented as a case study. This paper provides the implementation of the transmitter and the receiver of the PDSCH in LTE using SDSoC tool and selects a platform that meets performance metrics constraints.     

Design of a frequency selective structure with inhomogeneous substrates as a thermophotovoltaic filter

In this paper, the design of a thermophotovoltaic (TPV) filter with high-pass characteristics is presented. The filter is in the form of a frequency selective structure (FSS) with cascaded inhomogeneous dielectric substrates. The goal is to allow for more design flexibility using dielectric periodic structures to deliver a sharper filter response. Therefore, the primary focus is to design a periodic material substrate composition (supporting FSS elements) using a topology optimization technique known as the density method. The design problem is formulated as a general nonlinear optimization problem and sequential linear programming is used to solve the optimization problem with the sensitivity analysis based on the adjoint variable method for complex variables. A key aspect of the proposed design method is the integration of optimization tools with a fast simulator based on the finite element-boundary integral method. The capability of the design method is demonstrated by designing the material distribution for a TPV filter subject to pre-specified bandwidth and compactness criteria.     

Design of CVT-Based Hybrid Passenger Cars

In this paper, the hybridization of a small passenger car equipped with a continuously variable transmission (CVT) is investigated. Designing a hybrid drive train is a multiobjective design problem. The main design objectives are fuel consumption, emissions, and performance. However, it is difficult to find a global optimal integral design solution due to the interdependence of design choices (parameters) regarding the drive-train topology, component sizes, component technologies, and control strategy, as well as the unknown sensitivity of the design objectives to the design parameters. In this paper, a parametric optimization procedure is presented to solve the design problem, where the main design objective is fuel consumption. The effects of parameter variation on fuel consumption have been investigated. Furthermore, a reduced hybrid drive-train model is introduced, with which the effects of design parameter variation is very quickly studied with an average error of less than 1.6%.      

A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer’s knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.     

A CMOS IC for Gb/s Viterbi decoding: system design and VLSIimplementation

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization. The achievable speed of conventional Viterbi decoders (VD's) is limited by the inherent nonlinear add-compare-select (ACS) recursion. The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricated ASIC's for high speed Viterbi decoding using the “minimized method” (MM) parallelized VA. We particularly emphasize the interaction between system design, architecture and VLSI implementation as well as system partitioning issues and the resulting requirements for the system design flow. Our design objectives were 1) to achieve the same decoding performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC. With a minimum system configuration of four identical ASIC's produced by using 1.0 μ CMOS technology, the design objective of a decoding speed of 1.2 Gb/s is achieved. This means, compared to previous implementations of Viterbi decoders, the speed is increased by an order of magnitude     

基于LED光源的DLP光学引擎的光学设计

设计了一种基于LED光源照明系统的DLP背投电视光学引擎,样机以HD2+数字微镜(DMD),蝇眼透镜,X棱镜作为主要光学系统构件.介绍了基于光学扩展量etendue的光学系统设计方法,采用了蝇眼透镜阵列作为匀光方案来提高光能利用率和光源均匀度,分析了照明系统的工作原理和系统结构,并给出了仿真结果,样机在三组LED占空比为10:15:11的时序工作模式下白场输出光通量达到了112.3 lm,单色输出光通量分别为R.26.1 lm、G-51.4 lm、B-19.0 lm,光场均匀度小于±20%.