高介电常数栅极电介质材料的研究进展

随着半导体技术的飞速发展,作为硅基集成电路核心器件的MOSFET的特征尺寸正以摩尔定律的速度缩小.然而,当传统栅介质层SiO2的厚度减小到原子尺寸时,由于量子隧穿效应的影响,SiO2将失去介电性能,致使器件无法正常工作.因此,必须寻找新的高介电常数材料来替代它.目前,高介电常数材料是微电子行业最热门的研究课题之一.主要介绍了栅介质层厚度减小所带来的问题(即研究高介电常数材料的必要性)、新型栅电介质材料的性能要求,并简要介绍和评述了近期主要高介电常数栅介质材料的研究状况及其应用前景.     

Hf基高K栅介质材料研究进展

随着微电子技术的不断发展,MOSFET的特征尺寸已缩小至100nm以下,SiO2作为栅介质材料已不能满足技术发展的需求,因此必须寻求一种新型高K的介质材料来取代SiO2.当今普遍认为Hf基栅介质材料是最有希望取代SiO2而成为下一代MOSFET的栅介质材料.综述了高K栅介质材料的意义、Hf基高K栅介质材料的最新研究进展和Hf基高K栅介质材料在克服自身缺陷时使用的一些技术;介绍了一款由Hf基高K介质材料作为栅绝缘层制作的MOSFET.     

高K栅介质材料的研究现状与前景

论述了45～32nm技术节点下高K材料取代SiO2的必要性和基本要求,综述了高K栅介质中极具代表性的Hf基材料.研究表明,向HfO2中分别掺杂Al、si、Ta、N等形成的复合Hf基高K栅介质材料具备较Hfo2更加优异的物理结构、晶化温度、热力学稳定性以及电学特性,但与此同时也存在如何优化掺杂量、沟道载流子迁移率下降以及中间层引起的界面退化等难题.针对这些挑战,探讨了新型"堆垛结构"和引起载流子迁移率下降的物理机制,展望了高K材料在未来先进COMS器件中的应用.     

英特尔公司的45nm高k／金属栅工艺

在近期于华盛顿举行的国际电子器件会议（IEDM）上,英特尔公司相关负责人披露了该公司有关45nm高k／金属栅加工流程的某些细节,但未告知有关pFET电极金属的关键“元件”。该公司采取的是“先高k,后金属栅”办法。依然要通过高温退火以激活介电层与金属栅之间的掺杂剂,可保持其pFET晶体管的电极有合适的功函数,使该pFET的工作速度比上一代工艺快15％。     

高k值HfO2栅介质材料电学特性的研究进展

随着Si-MOS集成电路的迅速发展,高k值栅介质材料将成为下一代MOS器件绝缘栅最有希望的候选材料.介绍了近年来HfO2栅介质材料在制备方法和电学特性方面的研究进展,提出了改善其电学特性的主要途径,其中包括非金属元素掺杂、构建组分渐变界面、设计准二元合金系统、制备堆垛积层结构、抑制界面层生长和选择适宜的电极材料等.     

电线电缆绝缘及护套材料的技术分析及质量控制

电线电缆产品需求量的不断增加,进一步加剧了市场竞争的激烈程度。各企业为在电线电缆行业中获得更大的市场份额,开始加大了对产品材料成本以及生产工艺等内容的研究力度。该文也将以此为中心,通过对电线电缆概况的介绍,对电线电缆绝缘与护套材料展开深度分析,期望能够为我国电线电缆产品生产与应用提供一些理论方面支持。     

非晶Er2O3高 k栅介质薄膜的制备及结构特性研究

采用高真空反应蒸发法在未加热的P型Si(100)衬底上实现了非晶Er2O3高k栅介质薄膜的生长.俄歇电子能谱证实薄膜组分符合化学剂量比. X射线衍射、反射式高能电子衍射和高分辨透射电子显微镜测量表明,不但原位沉积的薄膜足非晶结构,而且高真空700℃退火30min后样品仍保持了良好的非晶稳定性.原子力显微镜检测显示高真空退火有利于改善薄膜的表面形貌.退火后,Er2O3薄膜获得了平整的表面.电容.电压测试得到薄膜的有效介电常数为12.6,EOT为1.4nm,在1MV/cm时漏电流密度为8×10-4A/cm2.这些特征表明非晶Er2O3薄膜是一种较好的高k栅介质候选材料.     

高介电栅介质材料研究进展

传统的栅介质材料SiO₂不能满足CMOS晶体管尺度进一步缩小的要求, 因此高介电栅介质材料在近几年得到了广泛的研究, 进展迅速. 本文综述了国内外对高介电材料的研究成果, 并结合作者的工作介绍了高介电栅介质在晶化温度、低介电界面层、介电击穿和金属栅电极等方面的最新研究进展.     

Advanced CMOS device technologies for 45 nm node and below

We review and discuss the latest developments and technology options for 45 nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG) candidates for scaled CMOS technologies are fully silicided (FUSI) gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-V_T) are reported (17 ps at V_DD=1.1 V and 20 pA/μm I_off), meeting the ITRS 45 nm node requirement for low-power (LP) CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress) or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32 nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here.     

新一代栅介质材料--高K材料

介绍了微电子工业的发展趋势和SiO2作为CMOS栅介质减薄所带来的问题,从而引出对高K材料的需求,简单介绍了作为栅极介质的各种高介电常数材料的性能的比较及制备高K薄膜的主要方法,总结了一些高K材料的研究现状,论述了目前有待进一步解决的问题,并展望了高K材料的发展趋势.     

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices.In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics.In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed.The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4.Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.     

高k栅介质的研究进展

随着集成电路的飞速发展,半导体器件特征尺寸按摩尔定律不断缩小.SiO2栅介质将无法满足Metal-oxide-semniconductor field-effect transistor(MOSFET)器件高集成度的需求.因此,应用于新一代MOSFET的高介电常数(k)栅介质材料成为微电子材料研究热点.介绍了不断变薄的SiO2栅介质层带来的问题、对MOSFET栅介质材料的要求、制备高k薄膜的主要方法,总结了高k材料的研究现状及有待解决的问题.     

CMOS双层可变功函数金属栅技术

针对发展高速、低功耗CMOS电路,分析了CMOS技术对多层金属栅的要求;对于不同金属厚度的双层金属栅,利用MOS系统能带的变化得出半导体与多层金属功函数差取决于底层金属的功函数,这为只通过调节底层金属功函数以达到改变CMOS阈值电压提供了理论依据;利用不同厚度的双层金属系统能带变化分析获得,当多层金属栅的底层金属厚度小于其最大偶极层厚度时,功函数较厚膜材料变大,达到"厚度调变功函数"效应。     

高k栅介质薄膜材料研究进展

金属-氧化物-半导体场效应晶体管(MOSFET),要求其器件特征尺寸越来越小,当光刻线宽小于100nm尺度范围后,栅介质氧化物层厚度开始逐渐接近(1～1.5)nm,这时电子的直接隧穿而导致栅极漏电流随栅氧化层厚度的下降而指数上升,此外,当栅氧化层薄到一定程度后,其可靠性问题,尤其是与时间相关的击穿及栅电极中的杂质向衬底的扩散等问题,将严重影响器件的稳定性和可靠性.因此需要寻找一种具有高介电常数的新型栅介质材料来替代SiO2,在对沟道具有相同控制能力的条件下(栅极电容相等),利用具有高介电常数的介质材料(一般称为高k材料)作为栅介质层可以增加介质层的物理厚度,这将有效减少穿过栅介质层的直接隧穿电流,并提高栅介质的可靠性.本文介绍了高k栅介质薄膜材料的制备方法,综述了高k栅介质薄膜材料研究的应用要求及其研究发展动态.