Analytical threshold voltage model for ultrathin SOI MOSFETsincluding short-channel and floating-body effects

Short-channel effects (SCE) in ultrathin silicon-on-insulator (SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model for threshold voltage, including the kink effect, is presented. The proposed model accounts for (1) a general nonuniform channel doping profile, (2) the drain-induced V_th- lowering enhancement resulting from the interaction of (a) impact ionization, (b) floating-body, and (c) parasitic-bipolar effects. Good agreement between the proposed model and experimental data is demonstrated. Impact ionization and floating-body effects dominate V_th lowering for drain voltages larger than V_dk≃B_i.λ_i/3, where B_i is the impact ionization coefficient, and λ_i is the impact ionization length, a structural parameter which, for a single-drain SOI MOSFET, coincides with the SCE characteristic length λ     

Three mechanisms determining short-channel effects infully-depleted SOI MOSFETs

Mechanisms determining short-channel effects (SCE) in fully-depleted (FD) SOI MOSFETs are clarified based on experimental results of threshold voltage (V_T) dependence upon gate length, and analysis using a two-dimensional (2-D) device simulator. Drain-induced barrier lowering (DIBL) effect is a well known mechanism which determines the SCE in conventional bulk MOSFETs. In FDMOSFETs, two more peculiar and important mechanisms are found out, i.e., the accumulation of majority carriers in the body region generated by impact ionization, and the DIBL effect on the barrier height for majority carriers at the edge of the source near the bottom of the body. Due to these peculiar mechanisms, V_T dependence upon gate length in the short-channel region is weakened. It is also shown that floating body effects, the scatter of V_T, and transient phenomena are suppressed due to the SCE peculiar to FD MOSFETs     

Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (T/sub SI/) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the T/sub SI/ fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the T/sub SI/ fluctuation scattering are remarkably enhanced with reducing T/sub SI/, so that they could help explain the experimental mobility behavior.     

Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices

This paper presents a quantitative study on the device design for the control of threshold-voltage and the suppression of short-channel effects (SCEs) in ultrathin strained-silicon-on-insulator (strained-SOI) CMOSFETs in the sub-100-nm regime. A two-dimensional device simulation is used for this purpose, with emphasis on the impact of band offset in Si/SiGe heterostructures. For the control of threshold-voltage, the combination of the gate work function and the back gate bias is needed to obtain appropriate values of threshold-voltage in n- and p-channel MOSFETs and to suppress SiGe buried channels in p-channel MOSFETs with thicker strained-Si layers. Regarding SCEs, the importance and the necessity of thin SiGe layers are pointed out from the viewpoint of the influence of the higher permittivity of SiGe layers. It is shown that the SCEs of strained-SOI MOSFETs with thinner SiGe layers are almost the same level as those of unstrained-SOI.     

Sub-40 nm SOI V-groove n-MOSFETs

We present output and transfer characteristics of single-gated, 36 nm, 46 nm and 56 nm channel length SOI MOSFETs with a V-groove design. For the shortest devices we find transconductances as high as 900 μS/μm and drive currents of 490 μA/μm at V_gs - V _th=0.6 V. The V-groove approach combines the advantages of a controlled, extremely abrupt doping profile between the highly doped source/drain and the undoped channel region with an excellent suppression of short-channel effects. In addition, our V-groove design has the potential of synthesizing devices in the 10 nm range     

Fully depleted n-MOSFETs on supercritical thickness strained SOI

Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO/sub 2/ from relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically associated with exceeding this limit.     

Microwave performance of SOI n-MOSFETs and coplanar waveguides

The microwave performance of 1-μm gate-length n-MOSFETs fabricated on both SIMOX and BESOI substrates was measured. The process included a self-aligned silicide in an otherwise conventional MOS sequence. Initial optimization yielded devices with an f_max of 14 GHz on BESOI and 11 GHz on SIMOX. Coplanar waveguides (CPWs) were fabricated on substrates with resistivities from 4 to 4000 Ω-cm. A loss of 1.8 dB/cm at 2 GHz was demonstrated on the 4000-Ω-cm float-zone substrate     

Performance comparison of channel engineered deep sub-micrometer pseudo SOI n-MOSFETs

In this paper, with the help of extensive TCAD simulations, a novel channel and source/drain (S/D) impurity profile engineering has been proposed for pseudo SOI MOSFET structures in order to reduce their junction capacitances. It has been shown that this approach leads to improved performance and lower power dissipation for sub 100 nm CMOS technologies. These pseudo SOI structures studied in this work are referred to as the Source Drain On Depletion Layer (SDODEL) MOSFETs in the earlier studies. We have investigated DC characteristics and analog performance parameters in Single Halo SDODEL MOSFET, Double Halo SDODEL MOSFET and compared their performance with Double Halo MOSFETs (which will henceforth be referred to as Control MOSFETs) with extensive process and device simulations. Our results shows that, in Single Halo SDODEL MOSFET there is significant improvement in the intrinsic device performance for analog applications (such as device gain, g_m/I_D etc.) for the sub 100 nm technologies.     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Measurement and simulation of floating substrate effects on the intrinsic gate capacitance characteristics of SOI n-MOSFETs

The theoretical foundation of unique floating substrate effects, which have been observed experimentally, on the intrinsic gate capacitance characteristics in saturation of SOI N-MOSFETs, is clearly established using original two-dimensional numerical device simulations.<>     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

Integration of Gd silicate/TiN gate stacks into SOI n-MOSFETs

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high-k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO₂. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170 cm²/Vs have been found for GdSiO.     

Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique

A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.     

Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling

Low-frequency flicker noise in analog n-MOSFETs with 15-/spl Aring/ gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.     

Improvement of breakdown voltage in SOI n-MOSFETs using thegate-recessed (GR) structure

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain     

Radiation source dependence of performance degradation in thin gate oxide fully-depleted SOI n-MOSFETs

The degradation of the electrical performance of thin gate oxide fully depleted SOI n-MOSFETs and its dependence on the radiation particles are investigated. The transistors are irradiated with 7.5-MeV protons and 2-MeV electrons at room temperature without bias. The shift of threshold voltage and the coupling effect with the degraded opposite gate are clarified. A remarkable reduction of the floating body effects is observed after irradiation. The degradation of the extracted parameters is discussed by a comparison with the damage coefficients.     

On the electron mobility in ultrathin SOI and GOI

The mobility of electrons in ultrathin silicon-on-insulator (SOI) and germanium-on-insulator (GOI) is studied. Quantum simulations are carried out to calculate phonon-limited mobility based on the experimental data for bulk. Modulation of the electron population in different ladders is shown to have a constructive effect in (111) Ge, whereas in (100) Ge mobility drops monotonically with either increase of gate bias or by thinning the GOI film.     

Heating mechanisms of LDMOS and LIGBT in ultrathin SOI

Temperature rises due to self-heating in silicon-on-insulator (SOI) power devices may lead to performance degradation and reliability problems. This letter investigates the mechanisms and spatial distribution of heat generation in linearly graded SOI LDMOS and LIGBT devices. While Joule heating dominates in LDMOS devices, hole collection at the p-well-drift region junction contributes strongly to the heating of LIGBT's. Also, the presence of both Joule and recombination heating makes the heating profile more uniform in LIGBT's. These effects combine to yield a temperature rise in LIGBT's that is more uniform and lower on average than that in LDMOS devices     

Self-align recessed source drain ultrathin body SOI MOSFET

In this letter, a self-aligned recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOS technology is proposed and demonstrated. The thick diffusion regions of ReS/D are placed on a recessed trench, which is patterned on the buried oxide and go under the SOI film. The new structure reduces the parasitic S/D resistance without increasing the gate-to-drain Miller capacitance, which is the major advantage over the elevated S/D structure. Fabrication details and experimental results are presented. The scalability of the UTB MOSFETs and the larger design window due to reduced parasitics are demonstrated.