Ultrafast operation of Vth-adjustedp+-n+ double-gate SOI MOSFET's

To optimize the V_th of double-gate SOI MOSFET's, we fabricated devices with p⁺ poly-Si for the front-gate electrode and n⁺ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V_th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching

Ultranarrow and ideal rectangular cross section silicon(Si)-Fin channel double-gate MOSFETs (FXMOSFETs) have successfully been fabricated for the first time using [110]-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. The transconductance (g/sub m/) normalized by 2/spl times/(Fin height) is found to be as high as 700 /spl mu/S//spl mu/m at V/sub d/=1 V in the fabricated 13-nm-thick and 82-nm-high Si- Fin channel double-gate MOSFET with a 105-nm gate length and a 2.2-nm gate oxide. The almost-ideal S-slope of 64 mV/decade is demonstrated in a 145-nm gate length device. These excellent results show that the Si-Fin channel with smooth [111]-oriented sidewalls is suitable to realize a high-performance FXMOSFET. The short-channel effects (SCEs) are effectively suppressed by reducing the Si-Fin thickness to 23 nm or less.     

A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.     

Analytical threshold voltage model for ultrathin SOI MOSFETsincluding short-channel and floating-body effects

Short-channel effects (SCE) in ultrathin silicon-on-insulator (SOI) fully depleted (FD) MOSFETs are analyzed and an analytical model for threshold voltage, including the kink effect, is presented. The proposed model accounts for (1) a general nonuniform channel doping profile, (2) the drain-induced V_th- lowering enhancement resulting from the interaction of (a) impact ionization, (b) floating-body, and (c) parasitic-bipolar effects. Good agreement between the proposed model and experimental data is demonstrated. Impact ionization and floating-body effects dominate V_th lowering for drain voltages larger than V_dk≃B_i.λ_i/3, where B_i is the impact ionization coefficient, and λ_i is the impact ionization length, a structural parameter which, for a single-drain SOI MOSFET, coincides with the SCE characteristic length λ     

Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate

We report the first observation of threshold-voltage instability of single-crystal silicon (Si) thin-film transistors (TFTs) that are fabricated on low-temperature flexible plastic substrate. Single-crystal Si of 200-nm thickness is transferred from silicon-on-insulator (SOI) onto an indium-tin-oxide-coated polyethylene terephthalate host substrate after selectively removing the buried-oxide layer from the SOI. TFTs of n-type were then fabricated on the transferred single-crystal Si layer with 1.8-mum thick SU-8-2 epoxy as the gate dielectric layer. It is observed that the threshold voltage (V_th) of these TFTs shifts to higher and lower values under high positive and negative gate-voltage stress, respectively. A logarithmic time-dependence of the V_th shift at high bias stress was clearly indicated. These results suggest that the instability of the threshold voltage of the single-crystal Si TFTs is attributed to the charge trapping in the gate dielectric layer.     

Analytical threshold voltage model for short channel double-gateSOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V_th, we derived a model for V_th of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, ΔV_th, and subthreshold swing (S-swing) degradation with decreasing gate length L _G, and showed that we can design a 0.05-μm-L_G device with ΔV_th of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available     

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

Flexibly controllable threshold-voltage (V_th) asymmetric gate-oxide thickness (T_ox) four-terminal (4T) FinFETs with HfO₂ [equivalentoxidethickness(EOT)=1.4 nm] for the drive gate and HfO₂+thick SiO₂ (EOT=6.4-9.4 nm) for the V_th-control gate have been successfully fabricated by utilizing ion-bombardment-enhanced etching process. Owing to the slightly thick V_th-control gate oxide, the subthreshold slope (S) is significantly improved as compared to the symmetrically thin T_ox 4T-FinFETs. As a result, the asymmetric T_ox 4T-FinFETs gain higher I_on than that for the symmetrically thin T_ox 4T-FinFETs under the same I_off conditions     

Modeling of $V_{rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

A threshold-voltage (V_th) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The V_th shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the V_th shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.     

Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs

The inhomogeneity of Schottky-barrier (SB) height Phi_B is found to strongly affect the threshold voltage V_th of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness t_OX and SOI body thickness; the contribution of inhomogeneity to the V_th variation becomes less pronounced with smaller t_OX and/or larger t_si . Moreover, an enhanced V_th variation is observed for devices with dopant segregation used for reduction of the effective Phi_B . Furthermore, a multigate structure is found to help suppress the V_th variation by improving carrier injection through reduction of its sensitivity to the Phi_B inhomogeneity. A new method for extraction of Phi_B from room temperature transfer characteristics is also presented.     

Impact of the vertical SOI `DELTA' structure on planar devicetechnology

A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance     

Improved stability of short-channel hydrogenated N-channelpolycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide

Stability has been investigated for short-channel hydrogenated n-channel polycrystalline thin-film transistors (poly-Si TFTs) with very thin (12 nm) electron cyclotron resonance (ECR) N₂O-plasma gate oxide. The TFTs show negligible changes in the electrical characteristics after hot-carrier stresses, which is due to the highly reliable interface and gate oxide. The hydrogenated TFTs with 3-μm gate length TFTs exhibit very small degradation (ΔV_th<15 mV) under hot-carrier stresses and Fowler-Nordheim (F-N) stress (ΔV_th=₈₁ mV, ΔGm/Gm=2.2%, ΔS/S=4.7%)     

Counter doping into uniformly and heavily doped channel region ofsub-0.1 μm SOI MOSFETs

We proposed counter doping into a heavily and uniformly doped channel region of SOI MOSFETs. This enabled us to suppress the short channel effects with proper threshold voltage V_th and to eliminate parasitic edge or back gate transistors. We derived a model for V_th as a function of the projected range, Rp and dose, Φ_D, of the counter doping, and showed that V_th is invariable even when the as-implanted counter doping profile redistributes. Using this technology, we demonstrated a V_th roll-off free 0.075 μm-L_Geff nMOSFET with low off-state current     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.     

Clarification of floating-body effects on drive current and shortchannel effect in deep sub-0.25 μm partially depleted SOIMOSFETs

We point out for the first time that floating-body effects cause the reduction of the saturation drive current in partially depleted (PD) Sol MOSFETs. It is demonstrated that when the channel concentration of the SOI MOSFETs is set higher in order to suppress the increase of the off current caused by floating-body effects, the drive current decreases due to the large body effect. In the conventional SOI structure where the source-drain junction is in contact with the buried oxide, the 0.18 μm floating PD SOI MOSFET suffers around 17% decrease in the drive current under the same threshold voltage (V_th) in comparison with body-fixed one. However, floating ID SOI MOSFETs show smaller V_th-roll-off. Further considering the short channel effect down to the minimum gate length of 0.16 μm, the current decrease becomes 6%. Also, we propose a floating PD SOI MOSFET with shallow source-drain junction (SSD) structure to suppress the floating-body effects. By using the SSD structure, we confirmed an increase in the drive current     

Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

The threshold voltages V_th of the body-tied double/triple-gate MOSFETs (bulk FinFETs) implemented on bulk silicon (Si) wafers were modeled systematically and compared with data obtained from 3-D device simulation. The threshold-voltage behaviors of the bulk FinFETs were modeled, for the first time, based on charge sharing. For the simplified V_th model, we considered not only short-channel effect (SCE) and narrow-width effect but also 3-D charge sharing at the corner. Only one fitting parameter is introduced to reflect the SCE in the fin body. The model predicted the V_th behavior with fin body thickness, body doping concentration, gate height, gate length, and corner shape of the fin body well. Our compact model makes an accurate prediction of V_th and shows good agreement with 3-D simulation data     

Study of Random-Dopant-Fluctuation (RDF) Effects for the Trigate Bulk MOSFET

A study of random-dopant-fluctuation (RDF) effects on the trigate bulk MOSFET versus the planar bulk MOSFET is performed via atomistic 3D device simulation for devices with a 20 nm gate length. For identical nominal body and source/drain doping profiles and layout width, the trigate bulk MOSFET shows less threshold voltage (V_th) lowering and variation. RDF effects are found to be caused primarily by body RDF. The trigate bulk MOSFET offers a new method of V_TH adjustment, via tuning of the retrograde body doping depth, to mitigate tradeoffs in V_TH variation and short-channel effect control.     

Short-channel effect improved by lateral channel-engineering indeep-submicronmeter MOSFET's

The normal and reverse short-channel effect of LDD MOSFET's with lateral channel-engineering (pocket or halo implant) has been investigated. An analytical model is developed which can predict V_th as a function of L_eff, V_DS, V_BS, and pocket parameters down to 0.1-μm channel length. The new model shows that the V_th roll-up component due to pocket implant has an exponential dependence on channel length and is determined roughly by (N_p)^¼L_p. The validity of the model is verified by both experimental data and two-dimensional (2-D) numerical simulation. On the basis of the model, a methodology to optimize the minimum channel length L_min is presented. The theoretical optimal pocket implant performance is to achieve an L_min approximately 55~60% that of a uniform-channel MOSFET without pocket implant, which is a significant (over one technology generation) improvement. The process design window of pocket implant is analyzed. The design tradeoff between the improvement of short-channel immunity and the other device electrical performance is also discussed     

Partial Crystallization of HfO2 for Two-Bit/Four-Level SONOS-Type Flash Memory

The nonvolatile memory properties of the partially crystallized HfO₂ charge storage layer are investigated using short-channel devices of gate length L_g down to 80 nm. Highly efficient two-bit and four-level device operation is demonstrated by channel hot electron injection programming and hot hole injection erasing for devices of L_g > 170 nm, although the reduction of the memory window is observed for devices of L_g < 170 nm. A memory window of 5.5 V, ten-year retention of V_th clearance larger than 1.5 V between adjacent levels, endurance for 10⁵ programming/erasing cycles, and immunity to programming disturbances are demonstrated. Flash memory with partially crystallized HfO₂ shows a larger memory window than HfO₂ nanodot memory, assisted by the enhanced electron capture efficiency of an amorphous HfO₂ matrix, which is lacking in other types of reported nanodot memory. The scalability, programming speed, V_th control for two-bit and four-level operation, endurance, and retention are also improved, compared with NROM devices that use a Si₃N₄ trapping layer.     

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.