Addressing Cu/Low-$k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies

Low-$k$ dielectrics, which are beneficial for chip resistance–capacitance ($RC$) delay improvement, crosstalk-noise minimization, and power-dissipation reduction, are indispensable for the continuous scaling of advanced VLSI circuits, particularly that of high-performance logic circuits. In this paper, several critical challenges for Cu/low-$k$ time-dependent dielectric-breakdown (TDDB)-reliability qualification will be reviewed. First, a low-$k$ TDDB field-acceleration model and its determination will be discussed. Second, the macroscopic interconnect line-to-line spacing variation across the wafer and the microscopic line-to-line spacing nonuniformity induced by line-edge roughness within the same test structure and their impacts on low- $k$ TDDB reliability will be carefully examined. The Weibull shape-parameter dependence on applied stress voltage due to such global and local spacing variations will be analyzed. Finally, the moisture effect on low-$k$ TDDB and capacitance stability as an example of the impact from process integration will be reported, demonstrating that low-$k$ TDDB is sensitive to back-end-of-the-line integration.      

Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

A high-voltage lateral double diffused metal–oxide–semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-$k$ dielectric (LK PSOI) is proposed. The low-$k$ value enhances the electric field strength in the dielectric $(E_{I})$. The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the $E_{I}$ and BV of LK PSOI with $k_{I} = hbox{2}$ are enhanced by 74% and 19%, respectively.      

Novel Dielectric-Constant Evaluation Method for Low-$k$ Multilevel Metallization Structures in ULSI

Precise evaluation of the dielectric constants of low- $k$ interlayer dielectrics in ULSI is essential in order to analyze the effects of their fabrication process and their structure on their $k$ -values. However, this is difficult to achieve in complicated multilayer structures with various kinds of stacked films having different physical properties. To address this problem, we have developed a novel evaluation method that makes it possible to precisely analyze the effects of structure and fabrication process on the $k$ -values of dielectrics.      

The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

Optimal $ Sigma Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis

This paper presents a comparative study of $Sigma Delta$ modulators for use in fractional-$ {N}$ phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.      

Analytical Model of $I$– $V$ Characteristics of Arbitrarily Shallow p-n Junctions

For the first time, an analytical model of arbitrarily shallow p-n junctions is presented. Depending on the junction depth, electrical characteristics of ultrashallow p-n junctions can vary from the characteristics of standard Schottky diodes to standard deep p-n junctions. This model successfully unifies the standard Schottky and p-n diode expressions. In the crossover region, where the shallow doping region can be totally depleted, electrical characteristics phenomenologically substantially different from typical diode characteristics are predicted. These predictions and the accuracy of the presented model are evaluated by comparison with the MEDICI simulations. Furthermore, ultrashallow $hbox{n}^{+}$-p diodes were fabricated, and the anomalous behavior in the crossover regime was experimentally observed.      

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T _ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.     

Eigendecomposition of Images Correlated on $S^{1}$, $S^{2}$, and $SO(3)$ Using Spectral Theory

Eigendecomposition represents one computationally efficient approach for dealing with object detection and pose estimation, as well as other vision-based problems, and has been applied to sets of correlated images for this purpose. The major drawback in using eigendecomposition is the off line computational expense incurred by computing the desired subspace. This off line expense increases drastically as the number of correlated images becomes large (which is the case when doing fully general 3-D pose estimation). Previous work has shown that for data correlated on S ¹ , Fourier analysis can help reduce the computational burden of this off line expense. This paper presents a method for extending this technique to data correlated on S ² as well as SO(3) by sampling the sphere appropriately. An algorithm is then developed for reducing the off line computational burden associated with computing the eigenspace by exploiting the spectral information of this spherical data set using spherical harmonics and Wigner-D functions. Experimental results are presented to compare the proposed algorithm to the true eigendecomposition, as well as assess the computational savings.     

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

A $Q$– $f$ Droop Curve for Facilitating Islanding Detection of Inverter-Based Distributed Generation

This paper presents a new method for islanding detection of distributed generation (DG) inverter that relies on analyzing the reactive power versus frequency (Q-f) characteristic of the DG and the islanded load. The proposed method is based on equipping the DG interface with a Q-f droop curve that forces the DG to lose its stable operation once an islanding condition occurs. A simple passive islanding detection scheme that relies on frequency relays can then be used to detect the moment of islanding. The performance of the proposed method is evaluated under the IEEE 1547 and UL 1741 antiislanding test configuration. The studies reported in this paper are based on time-domain simulations in the power systems computer-aided design (PSCAD)/EMTDC environment. The results show that the proposed technique has negligible nondetection zone and is capable of accurately detecting islanding within the standard permissible detection times. In addition, the technique proves to be robust under multiple-DG operation.     

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

MILC-TFT With High-$kappa$ Dielectrics for One-Time-Programmable Memory Application

In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-channel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high- $kappa$ dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage $V_{rm th} sim -hbox{0.78} hbox{V}$, excellent subthreshold swing $sim !!$ 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.      

Spectroscopy and Diode-Pumped Laser Experiments of LiLuF$_{bf 4}$:Tm$^{{bf 3}+}$ Crystals

In this work we report on the 2-${mbi mu}$m laser emission of LiLuF ${_{bf 4}}$ crystals doped with Thulium trivalent ions (Tm:LLF) at different doping density up to 16%. We will present our results regarding growth, absorption and emission spectroscopy, Judd–Ofelt analysis and room temperature diode pumping laser experiments as a function of the dopant density. The best result is 56% of slope efficiency, with a maximum output power of 280 mW. The emission wavelength ranges between 1985 and 2038 nm, exploiting the vibronic emission of Tm in LLF.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.