High Output Impedance Current-Mode Four-Function Filter with Reduced Number of Active and Passive Elements Using the Dual Output Current Conveyor

This paper reports a new single-input multi-output current-mode multifunction filter which can simultaneously realise LP, HP, BP and BR filter functions all at high impedance outputs. The circuit permits orthogonal adjustment of quality factor Q and ₀, employs only five grounded passive components and no element matching conditions are imposed. A second order all-pass function can easily be obtained. The passive sensitivities are shown to be low.     

基于电流反馈运算放大器的R-L和C-D阻抗的实现和应用

在集成电路的设计中,电感的集成是很困难的,因此,用有源电路来模拟电感很有必要。目前通用的做法是用电流传送器等有源器件实现的RL/CD阻抗电路,但基于电流反馈运算放大器实现的RL/CD阻抗电路却很少。结合相关的研究进展,用电流反馈运算放大器和一些无源元件实现了R-L(电阻-电感)和C-D(电容-频变负阻)系列阻抗电路。并且用该电路能实现高通?低通和高通滤波器功能。     

A New Transadmittance Type First-Order Allpass Filter Employing Single Third Generation Current Conveyor

A novel transadmittance (TA) mode first-order all-pass filter configuration is proposed. The proposed circuit uses a third generation current conveyor (CCIII), three resistors and a grounded capacitor. The output of the filter exhibits high output impedance so that the synthesized filter can be cascaded without additional buffers. The theoretical results are verified with PSPICE simulations using a CMOS realization of CCIII.     

IC Voltage to Current Transducers with Very Small Transconductance

This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 m 1 level below 15 _RMS and dynamic range of 63 dB. The power consumption is only 10 watts and the supply voltages are ± 1.5 volts.     

Differential voltage current controlled current conveyor with low-voltage operation capability

A novel differential voltage current controlled current conveyor topology is introduced in this article. It has the capability for operating in a low-voltage power supply environment and, also, offers resistorless filter realisations. The main attractive offered benefit is that the handling of AC signals is exclusively performed by nMOS transistors and, thus, the proposed element has capability for high-frequency operation. The performance of the proposed cell has been experimentally verified through the realisation of two 3rd-order filters, derived according to the leapfrog and component substitution methods. The filter topologies have been fabricated through the AMS 0.35 µm CMOS process.     

Insensitive voltage-mode and current-mode filters with easily modifiable transfer functions

Two configurations for 2^nd order current-mode filters are introduced. The circuits, which exhibit low values for their active and passive sensitivies are implemented from two current conveyors. They are easily cascadable because they exhibit zero input impedance. Two voltage-mode implementations are then deduced from them. Depending on the passive components used, the circuit will be either a 2^nd order or a 3^rd order filter. Both the current-mode and voltage-mode implementations are characterized by easily modifiable transfer functions, without affecting ₀ and Q.SPICE simulation results, which confirm the theoretical analysis, are given and discussed for current conveyors implemented in a translinear form.     

Chopper Modulators Using Current Conveyor Analogue Switches

The new CMOS Cowan, Ring, and Full-AM chopper modulators using current conveyor analogue switches are presented. The proposed chopper modulators use a square wave carrier current for controlling the transfer of a sine wave baseband voltage from nodes Y to nodes X, and the baseband currents from nodes X to nodes Z, of the current conveyors. The proposed chopper modulators are verified by simulating from the layout with a 0.5 μ m/level 49 MOSFET model of AMI obtained through MOSIS. With a supply voltage of ± 1.5 V, the operation range for the baseband voltage is between −300 mV and 300 mV. The operation range for the carrier current, bias currents for CCIIs, is ranged from ten to few hundred microamps. Using the carrier current of 20 μ A, the power consumption is not more than 0.8 mW in the operation range of the baseband voltage.     

Programmable SC Biquad Using One Single Capacitor Bank

This paper presents a new technique for programming SC circuits using a single time-multiplexed capacitor bank, achieving a significant reduction in capacitance area. Simulation and experimental results obtained with a programmable biquad low pass filter show the validity of the proposed method.Antonio Torralba was born in Seville, Spain. He received the electrical engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1983 and 1985, respectively. Since 1983, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Assistant professor, Associate Professor (1987), and Professor (1996). He has published 30 papers in journals and more than 80 papers in conferences. His research interests are in the design and modeling of low-voltage analog circuits, analog and mixed-signal design, analog to digital conversion, and electronic circuits and systems with application to control and communication.Alfredo Pérez Vega-Leal was born in Seville, Spain. He received the Electrical Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1998 and 2003, respectively. Since 1995, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, as research student and became an Associate Professor in 1999. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion.Ramón González Carvajal was born in Seville, Spain. He received the Electrical Engineering and Ph.D. degrees from the University of Seville, Seville, Spain, in 1995 and 1999, respectively. Since 1996, he has been with the Department of Electronic Engineering, School of Engineering, University of Seville, where he has been an Associate Professor (1996), and Professor (2002). He has published more than 100 papers in International Journals and Conferences. His research interests are related to low-voltage low-power analog circuit design, A/D and D/A conversion, and analog and mixed signal processing.     

Tunable Ladder-Type Realization of Current-Mode Elliptic Filters

It is shown that a new series FDNR-R equivalent circuit using current controlled current conveyors (CCCIIs) allows effective realization of jω-axis zeros which are known to complicate the active implementation of ladder-type elliptic filters. The resulting ladder-type elliptic filter employs all grounded capacitors while keeping the number of active elements small. Also, the filter parameters are electronically tunable, which is important from integration point of view.     

Current-Mode Universal Filters Using Current Conveyors: Classification and Review

Several current-mode universal filters are reviewed. The filters are classified in two classes. The class I filters have floating passive elements, whereas class II filters have all resistors and capacitors grounded. Each class of filters includes two subclasses based on the filter’s capability to have independent control of the filter quality factor or not. The effects of nonideal second generation current conveyors are briefly discussed. Spice simulations using BSIM3 version 3.1 parameters, feature size 0.5 μm from MOSIS, are given, and a detailed comparison table is included.     

Analysis of the Noise Characteristics of CMOS Current Conveyors

The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches to an optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors and current sources, and with the class AB design, the current mirror and current source noise can be reduced by using small values of bias current without compromising the maximum available output current.     

Current‐Mode Electronically Tunable Universal Filter Using Only Plus‐Type Current Controlled Conveyors and Grounded Capacitors

In this paper we present a new current‐mode electronically tunable universal filter using only plus‐type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions—all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters ω₀ and ω₀ / Q. No element matching conditions are imposed. Both its active and passive sensitivities are low.     

Realization of current-mirror filters with large time-constants

A novel scheme for realizing large time-constants in analog filters, using current-mirrors as active elements, is introduced in this paper. Instead of employing conventional capacitor multipliers, the proposed concept is based on the realization of very low values of transconductance. This has been achieved through a linear compression of the input signal in order to achieve operation of the core in a reduced bias current. The expansion performed by the output stage preserves the gain of the whole system. The validity of the proposed scheme as well as the offered benefit have been verified through simulation results using the Analog Design Environment of the Cadence software.     

Design of Monolithic Tunable CMOS Band-Pass Filter Using Current Feedback Operational Amplifiers

We propose in this paper a tunable second order band-pass filter based on two CMOS current feedback operational amplifiers (CFOAs). The CFOA includes a novel offset compensation technique. A digital building block is implemented in the proposed band-pass filter to tune its central frequency. An important feature of the adopted tuning procedure is the ability to tune the filter without affecting other characteristics such as gain, phase and quality factor. The band-pass filter topology is validated with a configuration where the central frequency is tuned from 60 MHz to 95 MHz with frequency steps of 5 MHz. Measurements of the offset-compensated CFOA are promising, and simulation results of the CFOA-based band-pass filter using the 0.18 μ m CMOS process confirm our theoretical analysis.     

On the Realization of Current－Mode Continuous－Time Operational Transconductance Capacitance Filter

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FGMOS Current Mirror: Behaviour and Bandwidth Enhancement

This paper presents a high performance, resistively compensated low voltage current mirror using floating gate MOSFETs (FGMOS). The compensation technique desensitizes the output current and input compliance voltage with respect to the process generated variations in the threshold voltages of the mirroring transistors. Theoretical and simulation results exhibit an appreciable increase in bandwidth of the current mirror for this compensation technique. The operation of these circuits has been verified using PSpice simulations for 0.5 μ m CMOS technology at a supply voltage of ±0.75 V. A part of this paper has appeared in IEEE APCCAS 2002 and NSM 2003. S. Sharma was born on 6th July 1967 at village Bhagta, district Udhampur, J and K (India). He received MSc Physics (Electronics) degree from University of Jammu in 1991 and was awarded University Gold Medal. After qualifying NET (CSIR), he joined as Lecturer in 1995 in the department of Physics and Electronics of the same University. He is presently a Senior Lecturer and pursuing for Ph.D. degree in the area of Analog Integrated Circuits. He has eight papers published in National/International Conferences/Journals. He is a life member of IETE (India). S.S. Rajput was born on July 1, 1957, at village Bashir Pur, District Bijnor UP India. He received his B. E. in Electronics and Communication Engineering and M. E. in Solid State Electronics Engineering from University of Roorkee, Roorkee, India (Now IIT, Roorkee) in 1978 and 1981 respectively and was awarded University gold medal in 1981. He earned his Ph.D. degree from Indian Institute of Technology, Delhi in 2002 and his topic of research was “Low voltage current mode analog circuit structures and their applications”. He joined National Physical Laboratory, New Delhi, India as Scientist B in 1983, where he is presently serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include low voltage analog VLSI, instrument design for space applications, Digital Signal Processing, Fault tolerant design, and fault detection. He has chaired the many sessions in Indian as well as International conferences. He is Fellow member of IETE (India). He has been awarded best paper award for IETE Journal of Education for the year 2002. He has delivered many invited talks on Low Voltage Analog VLSI. Few tutorials have been presented in International Conferences on his Research Work. He has more than 30 publications in national and international journals. L.K. Mangotra was born on 14th April 1944 at Jammu, India. He received M.Sc. (Physics) from University of Kashmir in 1968 and Ph.D. (High Energy Physics) from University of Jammu in 1974. He worked as Assistant Director in Forensic Laboratory of J and K Govt. from 1974–78. He joined Physics Department, University of Jammu as Lecturer in 1978 and became Professor in 1988. He has 131 publications in International Journals and 41 papers in proceedings of International/National Conferences. He has number of visits to foreign Universities in connection with research and has been awarded various Fellowships. He is a member of various Professional/Academic/Administrative bodies. Presently, Prof. Mangotra is an Advisor to University of Jammu for Modernization of University Infrastructure and Principal Investigator for Jammu University and Coordinator of All India Universities in the International Collaborative research project “ALICE” in High Energy Physics sponsored by Department of Atomic Energy and Department of Science and Technology, Govt. of India. S.S. Jamuar was born on 27th November 1949. He received his BSc. Engineering Degree in Electronics and Communication from Bihar Institute of Technology, Sindri in 1967, M. Tech and Ph.D. in Electrical Engineering from Indian Institute of Technology, Kanpur, India in 1970 and 1977 respectively. He worked as Research Assistant, Senior Research Fellow and Senior Research Assistant from 1969 to 1975 at IIT Kanpur. During 1975–76, he was with Hindustan Aeronautics Ltd., Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT Kanpur, where he was involved in the design of various types of Laser Systems. He joined department of Electrical Engineering of IIT Delhi in 1977, where he became Professor in 1991. He is presently Professor in the department of Electrical and Electronic Engineering Department, Faculty of Engineering, University Putra Malaysia, Malaysia. His area of research interest includes Electronic Circuit Design, Instrumentation and Communication systems. He is recipient of Meghnad Saha Memorial Award 1976 from IETE, Distinguished Alumni Award from BIT Sindri in 1999. Dr. Jamuar is senior member of IEEE and Fellow member of IETE (India). He is presently the Chair for CASS Chapter of IEEE Malaysia Section.     

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent corner error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 m CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.     

Universal Series and Parallel Immittance Simulators Using Four Terminal Floating Nullors

Most of the presented immittance simulator topologies in the literature realize certain types of inductor–resistor–capacitor combinations using the same configuration. In this study, a series and a parallel immittance simulator employing FTFNs in its most general form are introduced. The presented circuits are universal and able to simulate series and parallel (±G), (±L), (±C) for which all values are independently adjustable. The simulator circuits do not require any component matching constraint, except for the realization of pure inductance. Strong reduction in the number of active and passive elements is possible for special cases. The performance of the proposed universal immittance simulators is demonstrated on two chosen typical application examples by PSPICE simulations.     

Realization of n‐th Order Voltage Transfer Function Using a Single Operational Transresistance Amplifier

4 new configuration to realize the most general n‐th order voltage transfer function is proposed. It employs only one operational transresistance amplifier (OTRA) as the active element. In the synthesis of the transfer function, the RC:–RC decomposition technique is used. To the best of the author's knowledge, this is the first topology to be used in the realization of an n‐th order transfer function employing a single OTRA.     

一种新型电流模式连续时间波有源滤波器

以波接地电容为基本模块，提出了用电流镜和接地电容实现的电流 模式连续时间波有源滤波器。设计显示这种波器比基 于电流程分设计的电路具有比较好的通常特性。