A self-terminating low-voltage swing CMOS output driver

A CMOS output pad driver circuit is described that automatically series-terminates a driven line in the line's characteristic impedance. The circuit has advantages in speed, power, and size over conventional designs. The key idea is the use of emitter-coupled logic (ECL) compatible low-voltage swings for signaling, combined with the use of the driver transistor as both a switch and as a termination resistor. An on-chip measurement circuit dynamically adjusts the impedance of the driver to match the impedance of an external reference impedance standard, allowing the circuit to compensate for both chip and board level fabrication variations     

一种具有预驱动电路的低抖动LVDS驱动器

传统LVDS驱动器由于电源不稳定、驱动器与传输线之间阻抗不匹配等不良因素的影响,输出波形会出现抖动,质量下降.在传统LVDS驱动器的基础上,设计了一种新颖的LVDS驱动电路.该电路采用预驱动技术,控制输出电压的翻转和减少总输入电容,输出波形较为平滑.采用0.18μm工艺对电路进行仿真.结果显示,电路输出波形摆幅为0.345 V,输出共模电压为1.17V,总输入电容为72 fF.     

2.5 Gb/s laser-driver GaAS IC

A laser-diode driver GaAs IC incorporating an optional NRZ/RZ (non-return-to-zero/return-to-zero) conversion facility, having ECL (emitter-coupled logic) and SCFL (source-coupled FET logic)-compatible inputs and providing a 0-60-mA adjustable output current into a 50-Ω/5-V termination at bit rates up to 2 Gb/s NRZ and maintaining a clear eye opening of 50 mA at 2.5 Gb/s NRZ bit rate has been designed, using a commercial 1-μm gate-length (F_τ=12 GHz) GaAs MESFET foundry service. The high maximum output current is obtained by implementing the output driver as a cascode differential amplifier. The logic circuitry implemented using a novel, DCAL (diode-clamped active-load) SCFL family, which is based on gate-width scaling rather than on absolute values, so that the on-chip logic voltage swing is less sensitive to process variations than conventional SCFL. A 60% improvement in noise margin is also obtained. To verify laser driving performance a back-to-back optical-fiber transmission experiment was performed, giving good optical eye diagrams at 2.5 Gb/s. The electrooptical interplay between laser-diode driver and laser-diode has been demonstrated using SPICE simulations     

A 15 Gbps-NRZ,30 Gbps-PAM4,120 mA laser diode driver implemented in 0.15-an GaAs E-mode pHEMT technology

This paper presents the design and testing of a 15 Gbps non-return-to-zero (NRZ),30 Gbps 4-level pulse amplitude modulation (PAM4) configurable laser diode driver (LDD) implemented in 0.15-μm GaAs E-mode pHEMT technology.The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage.The output transmission-line back-termination,which absorbs signal reflections from the imperfectly matched load,is performed passively with on-chip 50-Ω resistors.The proposed 30 Gbps PAM4 LDD is implemented by combining two 15 Gbps-NRZ LDDs,as the high and low amplification paths,to generate PAM4 output current signal with levels of 0,40,80,and 120 mA when driving 25-Ω lasers.The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD.The measurement results show clear output eye diagrams at speeds of up to 15 and 30 Gbps for the NRZ and PAM4 drivers,respectively.At a maximum output current of 120 mA,the driver consumes 1.228 W from a single supply voltage of-5.2 V.The proposed driver shows a high current driving capability with a better output power to power dissipation ratio,which makes it suitable for driving high current distributed feedback (DFB) lasers.The chip occupies a total area of 0.7 × 1.3 mm2.     

A Low-Dropout Regulator for SoC With Q-Reduction

A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (V_THN ap 0.55 V and |V_THP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current     

High voltage output circuit using n- and n-LDMOSFET with thick gate oxide for PDP driver IC

A novel high voltage output circuit with thick-gated LDMOSFETs is proposed to reduce the chip size and to improve the switching speed for the plasma display panels (PDP) driver IC. The chip size of the PDP driver IC using the proposed output circuit is reduced by 35% with a similar falling time compared with the conventional one. The falling time of the proposed output circuit is about 2.5 times faster than that of the conventional one under the same size when the supply voltage and load capacitance are 180 V and 100 pF, respectively.     

Effective Radii of On-Chip Decoupling Capacitors

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.     

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.      

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

A novel energy-recovery sustaining driver for plasma display panel

A novel energy-recovery driver is proposed to drive a plasma display panel (PDP) in the sustaining operation. The proposed circuit uses the parallel resonance between the inductor and the intrinsic capacitance of PDP to mainly recover the energy lost by the capacitive displacement current of the PDP. The parasitic resonance caused by the parasitic inductance and the stray capacitance is prevented greatly. A 34-in AC PDP equipped with the proposed driving circuit, operated at 100 kHz, is investigated. In addition, some prior work is shown in this paper for comparison, in which the power consumption of driving the same 34-in panel is measured. The experimental results show that the proposed driver has a low-cost structure and better performance than the prior ones.     

A 1.2-μm BiCMOS sample-and-hold circuit with aconstant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/μs, -510 V/μs) slew rate and features a `built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V_p-p 20-MHz sine wave sampled at 100 MHz     

一种片内集成飞电容的自适应开关电容DC-DC

提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波＜40 mV     

Precision measurement technique of integrated MOS capacitor mismatching using a simple on-chip circuit

A precision measurement technique of the capacitor mismatchings of integrated circuits has been required, that is insensitive to parasitic capacitors on the chip, stray capacitors in measurement circuits, and external noises. A new ac measurement technique is developed here that uses an on-chip source-follower circuit and a simple algorithm. The source-follower circuit lowers the output impedance and thereby excludes the effects of external noises and stray capacitors in measurement circuits. In the present technique, capacitively divided ac voltage after the bandpass filter is measured in two steps by exchanging the terminals of the serial capacitors using external switches. Capacitor mismatching, defined by the relative capacitance toleranceDelta C/C, is derived as the ratio of the difference between the two measured voltages to their average. This derivation significantly reduces errors arising from parasitic capacitors on the chip, the nonlinearity of the source-follower circuit, and the pulse wave that can give the gate bias voltage of the source-follower transistor. The measurement error is estimated to be, in the worst case, 0.1 percent ofDelta C/C.     

片上带隙基准电压源参数快速确定方法

片上带隙基准电压源输出特性的偏差导致集成电路片上电源模块输出存在0~0.3 V的误差。文中对片上电源模块误差产生原因进行了研究,提出一种输出可调的带隙基准电压源外部电路设计方案来实现片上电源模块精确输出,并对电路参数确定方法进行了研究。该电路通过对片上带隙基准电压源后端分压电阻进行参数矫正实现对电源模块输出的精确调整。根据电流相等原理建立数学模型,通过测量两组固定参数电源模块输出数据,代入模型计算实现参数快速确定。实际测试数据证明,该电路可实现片上电源模块精确输出,误差仅为±0.02 V,满足实际应用需求。     

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred, as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low power consumption. A point-to-point link on a 90 nm CMOS test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.      

MOSFET寄生电容对E类功率放大器影响的研究

针对Class-E功率放大器传输效率受MOSFET寄生电容的影响,提出了一种提高传输效率的方法。通过调节RLC回路中串联谐振电容的数值,提高旁路电容的数值,调节负载回路,使其超过MOSFET自身的输出寄生电容,以达到提高输出效率的目的。计算及仿真结果表明该方法在13.56 MHz下,可以将Class-E的旁路电容的值提高到120～160 pF,大大超过了IRF510的102.98 pF的寄生输出电容。最后,通过MSO3012混合信号示波器测量电路的传输效率,并对解决方案评估和改进,将Class-E的能量传输效率从改进前的37.1%提高到改进后的54.4%。据此,实现了Class-E在神经假体中数据与能量传输的应用。     

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm~2.     

Full-swing CMOS output driver using on-chip capacitors, with fastrise time and small overshoot

A full-swing CMOS output driver with a fast rise time and a small overshoot was designed by using a high-order LRC scheme including on-chip capacitors. This high-order scheme eliminates the trade-off limitation between rise time and overshoot of the conventional second-order full-swing CMOS output driver. SPICE simulation using a 0.25 μm 2.5 V CMOS process showed that this output driver worked successfully at a data rate up to 500 Mbit/s with a 50 pF load     

Overshoot-controlled RLC interconnections

How overshoot in the step response of a circuit involving an RLC line can be controlled using a combination of driver and line resistance that depends on the load capacitance is shown. The no-peak condition or its equivalent is used to relate line parameters to the driver and load impedances. This no-peak condition generalizes the impedance matching customarily used for lossless lines, i.e. it provides an alternative to the traditional choice R_D=√ L/C. The results allow improved circuit response without risk of overshoot, for example, by reduction of driver resistance below √L/C for cases where line resistance is unavoidable and/or where load capacitance is not negligible compared to line capacitance. The algebraic formulas derived are more effective than case-by-case numerical simulations for analyzing scaling and technology issues, whether on-chip, or at the packaging, board, or system levels