Evaluation of stereo correspondence algorithms and their implementation on FPGA

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.     

生物Reichardt运动检测器和感受域模板的 FPGA设计与实现

为了在图像处理中快速地实现运动检测和相机自身运动方式估算,引入了基于生物视觉机制的Reichardt运动检测器模型(EMD)和感受域模板.分析了Reichardt运动检测器模型的基本特性及其缺陷.为了克服模型上的主要缺陷,在应用中选择了一种优化模型,应用该模型可以得到较好的运动检测结果.同时,提出了基于苍蝇视觉系统的6个感受域模板,用以实现简单自身运动方式的估算,如相机自身的平移、旋转等.最后,在FPGA(FieldProgrammable Gate Array)平台上实现了相关的算法.实验结果表明,优化后的运动检测器可以快速地判断局部运动方向,感受域模板可实现在特定背景下的简单运动方式估算;对分辨率为256×256像素的输入图片,本设计中的FPGA系统可达到每秒350帧的处理速率,所产生的延时仅为0.25μs,达到了快速处理的要求.此模型可应用于实时的机器视觉系统,如进行障碍物检测、整体运动方式估算、UAV/MAV的稳定控制等.     

基于DSP Builder的OQPSK调制器设计及FPGA实现

提出了0QPSK调制器的全数字实现方案,基于DSP Builder完成了方案的建模仿真并进行了硬件验证,实验表明,所设计的调制器工作稳定、可靠,达到设计要求.     

基于小波变换的ECG信号压缩及其FPGA实现

小波变换在ECG信号处理中的应用得到了很多研究人员的关注。本文研究了5层5/3提升小波变换及其反变换的FPGA实现,并将其应用于ECG信号的压缩,在均方误差可控的范围内获得了较大的压缩比,并利用设计的硬核实现了信号的重建。     

一种基于FPGA的素域椭圆曲线标量乘结构

基于一种简化求商的高基Montgomery模乘流水化阵列结构,提出并实现了素域上椭圆曲线标量乘硬件结构。该结构采用修正的Jacobian坐标的点加和倍点算法以及Kaliski提出的Montgomery模逆的算法。实验结果表明,该结构与相关工作相比具有更好的性能。     

基于改进的CORDIC算法的FFT复乘及其FPGA实现

根据定点FFT中旋转因子所对应的CORDIC旋转方向可预先求解的特点,改进了CORDIC算法中旋转方向的计算方法,在节约乘法器资源的同时兼顾了速度与精度的要求,并基于改进的CORDIC算法,利用FPGA实现了这种FFT复乘模块。仿真结果表明该设计可行,具有一定的实际意义和应用前景。     

Learning and surface boundary feedbacks for colour natural scene perception

Boundary detection and segmentation are essential stages in object recognition and scene understanding. In this paper, we present a bio-inspired neural model of the ventral pathway for colour contour and surface perception, called LPREEN (Learning and Perceptual boundaRy rEcurrent dEtection Neural architecture). LPREEN models colour opponent processes and feedback interactions between cortical areas V1, V2, V4, and IT, which produce top-down and bottom-up information fusion. We suggest three feedback interactions that enhance and complete boundaries. Our proposed neural model contains a contour learning feedback that enhances the most probable contour positions in V1 according to a previous experience, and generates a surface perception in V4 through diffusion processes. We compared the proposed model with another bio-inspired model and two well-known contour extraction methods, using the Berkeley Segmentation Benchmark. LPREEN showed better performance than two methods and slightly worse performance than another one.     

High-performance implementation of regular and easily scalable sorting networks on an FPGA

The paper is dedicated to fast FPGA-based hardware accelerators that implement sorting networks. The primary emphasis is on the uniformity of core components, feasible combinations of parallel, pipelined and sequential operations, and the regularity of the circuits and interconnections. The paper shows theoretically, and based on numerous experiments, that many existing solutions that are commonly considered to be very efficient have worthy competitors that are better for many practical problems. We compared the even–odd merge and bitonic merge sorting networks (which are among the fastest known) with the even–odd transition network, which is often characterized as significantly slower and more resource consuming. We found that the latter is the most regular network that can be implemented very efficiently in FPGA, so we are proposing new, easily scalable hardware solutions and processing techniques based on this. Finally, the paper provides four main contributions and suggests: (1) a regular hardware implementation of resource and time effective architectures based on the even–odd transition network; (2) a pipelined implementation of even–odd transition networks; (3) a pre-processing technique that enables sorting to be further accelerated; (4) combinations of this technique with a merge sort, an address-based sort, a quicksort, and a radix sort.     

An FPGA implementation for neural networks with the FDFM processor core approach

This paper presents a field programmable gate array (FPGA) implementation of a three-layer perceptron using the few DSP blocks and few block RAMs (FDFM) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation results show that the 150 processor cores for 32-32-32 input–hidden–output layer perceptrons can be implemented in the FPGA using 150 DSP48 slices, 185 block RAMs and 9676 slices. It runs in 242.89 MHz clock frequency, and a single evaluation of 150 nodes perceptron can be performed 1.65 × 10⁷ times per second.     

FPGA implementation of Kalman filter for neural ensemble decoding of rat's motor cortex

High performance computation is critical for brain-machine interface (BMI) applications. Current BMI decoding algorithms are always implemented on personal computers (PC) which affect the performance of complex mapping models. In this paper, an FPGA implementation of Kalman filter (KF) algorithm is proposed as a new computational method. The neural ensemble activities are recorded from motor cortex of rats performing a lever-pressing task for water reward. Kalman filter, which is used for mapping neural activities to kinematic variables, is implemented both on PC (MATLAB-based) and FPGA. In FPGA architecture, the row/column-based method is adopted for the matrix operation instead of the traditional element-based method, parallel and pipelined structures are also used for efficient computation at the same time. The results show that the FPGA-based implementation runs 24.45 times faster than the PC-based counterpart while achieving the same accuracy. Such a hardware-based computational method provides a tool for high-performance computation, with profound implications for portable BMI application.     

利用对称性加速实序列FFT的方法及其FPGA实现*

针对工程实践中傅里叶变换的输入序列一般为实序列的情况,充分利用FFT（快速傅里叶变换）奇偶虚实的对称性质,提出了一种实序列FFT的加速算法。将2N点的实序列DFT转换为N点的复序列DFT,并行计算使运算量明显减少;并给出了基于FPGA的硬件实现方法。     

混沌吸引子及FPGA实现

提出了一个混沌系统,并利用理论和数值仿真的方法对系统的基本特性进行了分析。通过Lyapunov指数谱和分岔图,对系统在混沌、拟周期和周期轨之间的转换进行了分岔分析。为验证系统的混沌行为,在Matalab的Simulink下,利用DSP Builder设计了一个电路,并把它转换成VHDL语言程序,利用Quartus II下载到硬件电路中进行了实验,实验结果与计算机仿真结果完全一致。提出了一种基于FPGA平台和EDA开发工具的实现混沌吸引子的新方法。     

A real-time versatile roadway path extraction and tracking on an FPGA platform

This paper presents an algorithm for roadway path extraction and tracking and its implementation in a Field Programmable Gate Array (FPGA) device. The implementation is particularly suitable for use as a core component of a Lane Departure Warning (LDW) system, which requires high-performance digital image processing as well as low-cost semiconductor devices, appropriate for the high volume production of the automotive market. The FPGA technology proved to be a proper platform to meet these two contrasting requirements. The proposed algorithm is specifically designed to be completely embedded in FPGA hardware to process wide VGA resolution video sequences at 30 frames per second. The main contributions of this work lie in (i) the proper selection, customization and integration of the main functions for road extraction and tracking to cope with the addressed application, and (ii) the subsequent FPGA hardware implementation as a modular architecture of specialized blocks. Experiments on real road scenario video sequences running on the FPGA device illustrate the good performance of the proposed system prototype and its ability to adapt to varying common roadway conditions, without the need for a per-installation calibration procedure.     

基于双曲正弦函数的四翼忆阻混沌系统及其FPGA实现

采用双曲正弦函数忆阻器作为正反馈项,设计了一个具有4个翅膀的四维混沌模型。首先利用四阶龙格库塔算法对该系统进行数值求解,对系统的稳定性进行了分析,发现系统只有一个平衡点且为鞍点。对系统进行动力学分析,绘制了随系统参数变化的Lyapunov指数和分岔图,计算了系统的Lyapunov维数,得到了系统随参数变化时运动状态的变化情况,发现系统存在周期和混沌等多种运动形态。最后,利用FPGA设计了一个混沌电路系统,用示波器观察结果,发现与数值结果基本一致,为忆阻混沌系统在通信中的应用奠定了基础。     

Keccak算法|海绵结构|哈希算法|可重构|现场可编程门阵列

在分析研究Keccak算法的基础上,针对现有Keccak算法的硬件实现方案版本单一,应用不灵活的问题,设计了一种高性能可重构的Keccak算法硬件实现方案。实验结果表明:该方案在Xilinx 公司的现场可编程门阵列(FPGA)Virtex-5平台上的时钟频率可达214MHz,占用1607slices;该方案具有吞吐量高(9131Mbps),应用灵活性好,可支持4种不同参数版本的优点。     

An investigation of the modified direction feature for cursive character recognition

This paper describes and analyses the performance of a novel feature extraction technique for the recognition of segmented/cursive characters that may be used in the context of a segmentation-based handwritten word recognition system. The modified direction feature (MDF) extraction technique builds upon the direction feature (DF) technique proposed previously that extracts direction information from the structure of character contours. This principal was extended so that the direction information is integrated with a technique for detecting transitions between background and foreground pixels in the character image.In order to improve on the DF extraction technique, a number of modifications were undertaken. With a view to describe the character contour more effectively, a re-design of the direction number determination technique was performed. Also, an additional global feature was introduced to improve the recognition accuracy for those characters that were most frequently confused with patterns of similar appearance. MDF was tested using a neural network-based classifier and compared to the DF and transition feature (TF) extraction techniques. MDF outperformed both DF and TF techniques using a benchmark dataset and compared favourably with the top results in the literature. A recognition accuracy of above 89% is reported on characters from the CEDAR dataset.     

USB安全钥模型的构建与实现

针对目前密码设备存在的不足,构建了一种USB安全钥模型,给出了模型对应的硬件整体结构及其系统工作流程,并介绍了安全钥关键功能模块的具体实现.USB安全钥集中了多种传统密码设备的功能,因而可以代替目前使用的部分密码设备应用于电子商务、电子政务等的安全解决方案中.     

高性能MCU的FPGA原型验证系统研究与平台实现

本文研究并实现了一种基于Cortex-A7核的高性能MCU在FPGA原型阶段的验证平台。该设计研究可以针对高性能MCU芯片或其FPGA原型验证阶段的软硬件验证环境快速搭建,通过交互式、软硬件协同的方式对MCU芯片各个模块功能进行实时、可靠的功能验证。高效的FPGA原型验证可以提高MCU研发速度、缩短验证时间、提高验证效率、及时发现芯片设计的缺陷、缩短芯片研发周期。     

基于AVS的变字长解码器的设计及其FPGA验证

提出了一个完整的AVS变字长解码器的硬件架构,在设计中采用加入FIFO的方法构成流水结构,并尽量减少变字长解码器中各子模块的运行节拍,大大提高了系统的运行速度。本设计已经通了FPGA验证。该变字长解码器不仅可以成为其他AVS解码器的硬件加速器,同时由于视频编解码标准的相似性,稍加改动即可应用在其他的视频标准中。     

A modified three-surface elasto-plastic cap model and its numerical implementation

One of main problems in the numerical implementation of many elasto-plastic cap models is associated with the issue how to handle the corner regions, where loading surfaces intersect in non-smooth fashion. At these points elasto-plastic tangent operators could become singular which would cause considerable numerical difficulties. In this paper we present a modified elliptic cap model in which the surfaces intersect in a smooth manner and in this way there is no need for changing the original model parameters. Several numerical examples are presented which show a very good approximation of soil behavior and an excellent convergence of computed results for all possible stress paths.