Evaluation of stereo correspondence algorithms and their implementation on FPGA

The accuracy of stereo vision has been considerably improved in the last decade, but real-time stereo matching is still a challenge for embedded systems where the limited resources do not permit fast operation of sophisticated approaches. This work presents an evaluation of area-based algorithms used for calculating distance in stereoscopic vision systems, their hardware architectures for implementation on FPGA and the cost of their accuracies in terms of FPGA hardware resources. The results show the trade-off between the quality of such maps and the hardware resources which each solution demands, so they serve as a guide for implementing stereo correspondence algorithms in real-time processing systems.     

基于DSP Builder的OQPSK调制器设计及FPGA实现

提出了0QPSK调制器的全数字实现方案,基于DSP Builder完成了方案的建模仿真并进行了硬件验证,实验表明,所设计的调制器工作稳定、可靠,达到设计要求.     

基于小波变换的ECG信号压缩及其FPGA实现

小波变换在ECG信号处理中的应用得到了很多研究人员的关注。本文研究了5层5/3提升小波变换及其反变换的FPGA实现,并将其应用于ECG信号的压缩,在均方误差可控的范围内获得了较大的压缩比,并利用设计的硬核实现了信号的重建。     

基于改进的CORDIC算法的FFT复乘及其FPGA实现

根据定点FFT中旋转因子所对应的CORDIC旋转方向可预先求解的特点,改进了CORDIC算法中旋转方向的计算方法,在节约乘法器资源的同时兼顾了速度与精度的要求,并基于改进的CORDIC算法,利用FPGA实现了这种FFT复乘模块。仿真结果表明该设计可行,具有一定的实际意义和应用前景。     

High-performance implementation of regular and easily scalable sorting networks on an FPGA

The paper is dedicated to fast FPGA-based hardware accelerators that implement sorting networks. The primary emphasis is on the uniformity of core components, feasible combinations of parallel, pipelined and sequential operations, and the regularity of the circuits and interconnections. The paper shows theoretically, and based on numerous experiments, that many existing solutions that are commonly considered to be very efficient have worthy competitors that are better for many practical problems. We compared the even–odd merge and bitonic merge sorting networks (which are among the fastest known) with the even–odd transition network, which is often characterized as significantly slower and more resource consuming. We found that the latter is the most regular network that can be implemented very efficiently in FPGA, so we are proposing new, easily scalable hardware solutions and processing techniques based on this. Finally, the paper provides four main contributions and suggests: (1) a regular hardware implementation of resource and time effective architectures based on the even–odd transition network; (2) a pipelined implementation of even–odd transition networks; (3) a pre-processing technique that enables sorting to be further accelerated; (4) combinations of this technique with a merge sort, an address-based sort, a quicksort, and a radix sort.     

An FPGA implementation for neural networks with the FDFM processor core approach

This paper presents a field programmable gate array (FPGA) implementation of a three-layer perceptron using the few DSP blocks and few block RAMs (FDFM) approach implemented in the Xilinx Virtex-6 family FPGA. In the FDFM approach, multiple processor cores with few DSP slices and few block RAMs are used. We have implemented 150 processor cores for perceptrons in a Xilinx Virtex-6 family FPGA XC6VLX240T-FF1156. The implementation results show that the 150 processor cores for 32-32-32 input–hidden–output layer perceptrons can be implemented in the FPGA using 150 DSP48 slices, 185 block RAMs and 9676 slices. It runs in 242.89 MHz clock frequency, and a single evaluation of 150 nodes perceptron can be performed 1.65 × 10⁷ times per second.     

FPGA implementation of Kalman filter for neural ensemble decoding of rat's motor cortex

High performance computation is critical for brain-machine interface (BMI) applications. Current BMI decoding algorithms are always implemented on personal computers (PC) which affect the performance of complex mapping models. In this paper, an FPGA implementation of Kalman filter (KF) algorithm is proposed as a new computational method. The neural ensemble activities are recorded from motor cortex of rats performing a lever-pressing task for water reward. Kalman filter, which is used for mapping neural activities to kinematic variables, is implemented both on PC (MATLAB-based) and FPGA. In FPGA architecture, the row/column-based method is adopted for the matrix operation instead of the traditional element-based method, parallel and pipelined structures are also used for efficient computation at the same time. The results show that the FPGA-based implementation runs 24.45 times faster than the PC-based counterpart while achieving the same accuracy. Such a hardware-based computational method provides a tool for high-performance computation, with profound implications for portable BMI application.     

A real-time versatile roadway path extraction and tracking on an FPGA platform

This paper presents an algorithm for roadway path extraction and tracking and its implementation in a Field Programmable Gate Array (FPGA) device. The implementation is particularly suitable for use as a core component of a Lane Departure Warning (LDW) system, which requires high-performance digital image processing as well as low-cost semiconductor devices, appropriate for the high volume production of the automotive market. The FPGA technology proved to be a proper platform to meet these two contrasting requirements. The proposed algorithm is specifically designed to be completely embedded in FPGA hardware to process wide VGA resolution video sequences at 30 frames per second. The main contributions of this work lie in (i) the proper selection, customization and integration of the main functions for road extraction and tracking to cope with the addressed application, and (ii) the subsequent FPGA hardware implementation as a modular architecture of specialized blocks. Experiments on real road scenario video sequences running on the FPGA device illustrate the good performance of the proposed system prototype and its ability to adapt to varying common roadway conditions, without the need for a per-installation calibration procedure.     

USB安全钥模型的构建与实现

针对目前密码设备存在的不足,构建了一种USB安全钥模型,给出了模型对应的硬件整体结构及其系统工作流程,并介绍了安全钥关键功能模块的具体实现.USB安全钥集中了多种传统密码设备的功能,因而可以代替目前使用的部分密码设备应用于电子商务、电子政务等的安全解决方案中.     

高性能MCU的FPGA原型验证系统研究与平台实现

本文研究并实现了一种基于Cortex-A7核的高性能MCU在FPGA原型阶段的验证平台。该设计研究可以针对高性能MCU芯片或其FPGA原型验证阶段的软硬件验证环境快速搭建,通过交互式、软硬件协同的方式对MCU芯片各个模块功能进行实时、可靠的功能验证。高效的FPGA原型验证可以提高MCU研发速度、缩短验证时间、提高验证效率、及时发现芯片设计的缺陷、缩短芯片研发周期。     

An investigation of the modified direction feature for cursive character recognition

This paper describes and analyses the performance of a novel feature extraction technique for the recognition of segmented/cursive characters that may be used in the context of a segmentation-based handwritten word recognition system. The modified direction feature (MDF) extraction technique builds upon the direction feature (DF) technique proposed previously that extracts direction information from the structure of character contours. This principal was extended so that the direction information is integrated with a technique for detecting transitions between background and foreground pixels in the character image.In order to improve on the DF extraction technique, a number of modifications were undertaken. With a view to describe the character contour more effectively, a re-design of the direction number determination technique was performed. Also, an additional global feature was introduced to improve the recognition accuracy for those characters that were most frequently confused with patterns of similar appearance. MDF was tested using a neural network-based classifier and compared to the DF and transition feature (TF) extraction techniques. MDF outperformed both DF and TF techniques using a benchmark dataset and compared favourably with the top results in the literature. A recognition accuracy of above 89% is reported on characters from the CEDAR dataset.     

基于AVS的变字长解码器的设计及其FPGA验证

提出了一个完整的AVS变字长解码器的硬件架构,在设计中采用加入FIFO的方法构成流水结构,并尽量减少变字长解码器中各子模块的运行节拍,大大提高了系统的运行速度。本设计已经通了FPGA验证。该变字长解码器不仅可以成为其他AVS解码器的硬件加速器,同时由于视频编解码标准的相似性,稍加改动即可应用在其他的视频标准中。     

A modified three-surface elasto-plastic cap model and its numerical implementation

One of main problems in the numerical implementation of many elasto-plastic cap models is associated with the issue how to handle the corner regions, where loading surfaces intersect in non-smooth fashion. At these points elasto-plastic tangent operators could become singular which would cause considerable numerical difficulties. In this paper we present a modified elliptic cap model in which the surfaces intersect in a smooth manner and in this way there is no need for changing the original model parameters. Several numerical examples are presented which show a very good approximation of soil behavior and an excellent convergence of computed results for all possible stress paths.     

一种BCH(63,56)译码方法及其FPGA实现

BCH码是很好的线性纠错码类,具有严格的代数结构、构造方便、编码简单。本文提出一种符合CCSDS的BCH(63,56)译码方法,译码方法相对简单,便于硬件实现译码,并具有计算速度快、占用资源少的特点。译码采用Xilinx的Spar-tan3XC3S1500FPGA来实现,满足航天分包遥控的标准。     

RS-CC的级联编码设计及其嵌入式FPGA实现

分析了802.16e无线通信系统,针对设计过程中经常出现的数据信息不同步问题,提出了一种基于RS(64,48,8)+CC(2,1,7)+交织的级联编码设计方案.该方案利用功能模块化的设计理念,达到了在不增加译码复杂度的情况下实现有效而可靠的通信.通过将各级编解码模块化,利用FPGA技术实现了整个级联纠错编译码系统.实验结果表明,模块化的FPGA嵌入式设计不仅提高了系统的稳定性,还大大缩短了开发周期.     

OFDM低压电力线通信系统的符号同步及其FPGA实现

为采用FGPA技术可靠实现基于G3-PLC协议的OFDM电力线通信系统的符号同步,推导了符号同步偏差对G3-PLC系统性能的影响。针对传统符号同步算法存在的算法复杂、FPGA实现困难等缺点,根据G3-PLC系统的帧结构,提出了基于训练序列的新的符号同步算法。仿真结果和FGPA实现效果表明,该算法不仅能够有效地实现G3-PLC系统的符号同步,而且运算量小,硬件资源消耗少。     

基于FPGA的阵列乘法器的设计与实现

先对乘法器进行了分析,然后用现场可编程门阵列(F P G A)实现了阵列乘法器,并分析了设计原理。     

A modified pulse coupled neural network for shortest-path problem

Shortest-path problem is well-known optimization problem and has been studied by many authors in recent years. Typically it is solved by using the famous Dijkstra's algorithm, which would quickly provide a global optimization solution in most instances. However, as the problem scale increases, this method is inefficient and may consume a considerable amount of CPU time. Neural networks, which are massively parallel models, can solve this question easily. This paper presents a novel biological neural network based algorithm for the finding of the shortest path in large scale systems. The start neuron fires first, and then the firing event spreads out through the lateral connections among the neurons, like the propagation of a wave. Then the generated spiking wave spreads at a constant speed so that the time of travel between two neurons is proportional to the path length between them. The computational complexity of the algorithm is only related to the length of the shortest path, and independent of the number of existing paths in the graph. Simulation results show that the proposed method is more efficient than Dijkstra's in the larger scale systems.     

数字锁相环位同步器及其FPGA设计

首先详细介绍了超前滞后型数字锁相环从位流数据中恢复出位时钟的原理,分析了其结构参数对于环路性能的影响并加以改进,最后在FPGA中利用VHDL语言实现。仿真结果表明,设计的方案对于受到干扰的基带数据可以稳定、快速锁定。     

A user model neural network for a personal news service

User modelling has been widely applied to pedantic situations, where we are attempting to infer the user's knowledge. In teaching it is important to know that the user has mastered the elementary concepts before proceeding with the advanced topics. However, the application of user modelling to information retrieval demands a quite different type of user model. Here we construct a user model for browsing, where the user is uncertain of exactly which information he desires. This requires a more inexact and robust user model, that can quickly give guidance to the system. We propose a user model based on neural networks that can be constructed incrementally. Performance of the model shows some promise for this approach. We discuss the advantages and limitations of the approach and its implications for user modelling.