Fully integrated 5.35-GHz CMOS VCOs and prescalers

Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-μm CMOS process. One VCO uses p⁺/n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p ⁺/n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming ~7 mW power at V_DD=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V_DD and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V_DD=2.5 V     

一种全集成型CMOS LDO线性稳压器设计

设计了一种基于0.25μm CMOS工艺的低功耗片内全集成型LDO线性稳压电路。电路采用由电阻电容反馈网络在LDO输出端引入零点,补偿误差放大器输出极点的方法,避免了为补偿LDO输出极点,而需要大电容或复杂补偿电路的要求。该方法电路结构简单,芯片占用面积小,无需片外电容。Spectre仿真结果表明：工作电压为2.5 V,电路在较宽的频率范围内,电源抑制比约为78 dB,负载电流由1 mA到满载100 mA变化时,相位裕度大于40°,LDO和带隙电压源的总静态电流为390μA。     

5-GHz Low Phase-Noise CMOS VCO Integrated With a Micromachined Switchable Differential Inductor

A 5-GHz CMOS voltage-controlled oscillator (VCO) integrated with a micromachined switchable differential inductor is reported in a 0.18 mum radio frequency-CMOS-based microelectromechanical system technology. The power consumption of the core is about 8 mW at the supply voltage of 1.8 V. A total tuning range of 470 MHz (from 5.13 GHz to 5.60 GHz) is achieved as the tuning voltage ranging from 0 V to 1.8 V. In the practical tuning range, the measured phase noise performances at 1 MHz offset are less than -125 dBc/Hz and -126 dBc/Hz when the inductor switch is turned on and off, respectively. The figure-of-merit is better than -190 dB. When compared with a contrast VCO circuit that utilizes a standard switchable differential inductor, this oscillator reaches a phase noise improvement of around 3 dB as the switch is turned on. Around 1-dB on-off phase noise difference can be achievable.     

一种适用于IEEE802.15.4协议的全集成CMOS复数滤波器

复数滤波器是低中频结构接收机中的一个重要模块,起到镜像抑制的作用。该文针对IEEE802.15.4的低功耗要求,提出了一种可以灵活配置共模反馈模块的伪差分结构OTA,该OTA具有内部共模前馈和共模检测功能,适用于级联应用。基于该OTA结构实现了一个3阶巴特沃斯Gm-C复数滤波器,中心频率在1 MHz,带宽1.3 MHz,带内群延时波动小于0.16 s,镜像抑制能力满足IEEE802.15.4协议要求。该文还提出了一种频率调节方法,用于控制复数滤波器的中心频率,与传统的锁相环结构相比,该调谐电路结构简单,适合在低功耗应用场合。     

集成宽带VCO的低相噪设计

从VCO的相位噪声概念及原理分析入手,论述了集成宽带压控振荡器低相噪的设计方法和设计思路,进行了理论分析和数学模拟,并通过利用相关软件进行仿真、优化设计。获得了低相噪声的宽带振荡器,并给出了各频段集成宽带VCO最终达到的相位噪声指标。低相噪声集成VCO系列产品的成功研制极大地方便了系统设计师的电路设计,该自主研制的低相噪VCO已广泛应用于多种电子系统中,对系统关键电路的国产化、高性能化有着重要意义。     

一种低相位噪声CMOS晶体振荡器的设计

运用小信号等效模型和负阻分析法,对晶体振荡器的起振条件进行分析,并用Matlab进行了仿真验证。采用TSMC 0.18μm CMOS工艺,设计了一种基于Pierce三点式振荡器结构的14MHz晶体振荡电路。提出了一种新的幅度控制电路,提高了振荡器相位噪声性能,并降低了功耗。仿真结果表明,振荡器的相位噪声达到-129.5dBc/Hz@1kHz和-143.658dBc/Hz@10kHz,具有优良的低相位噪声特性。     

一种5.7 GHz CMOS 全集成低噪声放大器的设计

提出并设计了一种可以完全单片集成的5.7 GHz低噪声放大器(LNA)。该电路结构利用MOSFET自身的栅寄生电阻,通过简单的LC网络变换实现输入匹配;并采用跨阻结构,实现输出匹配。该电路采用TSMC 0.35μm CMOS工艺,用ADS模拟软件进行分析与优化。结果表明,设计的低噪声放大器,其增益为11.34 dB,噪声系数为2.2 dB,功耗12 mW,输入反射系数-33dB,线性度-4 dBm。     

基于CMOS工艺的低相位噪声LC压控振荡器

介绍了一种用于锁相环型频率合成器的单片集成LC压控振荡器。该压控振荡器在传统的电路结构基础上进行了改进,在保证调谐范围的前提下,有效地降低了相位噪声。压控振荡器使用了片上集成螺旋电感,采用中芯国际(SMIC)0.35μm 1P6M混合信号CMOS工艺。测试结果表明,该压控振荡器的可调频率为3~3.55 GHz,在3.55 GHz中心频率附近的相位噪声达到-128 dBc/Hz(600 kHz),整个压控振荡器的工作电压为3.3 V,工作电流为13 mA。     

A 20MHz Low Phase-Noise 0.35μm CMOS Crystal Oscillator

The design procedure of a CMOS process integrating Colpitts cr(ystal oscillator is described in detail by using the tools of Matlab and advanced design system (ADS). The small-signal analysis is performed both in the viewpoint of negative resistance and positive feedback. The analysis of condition for reliable start-up of oscillation and design guides for low phase noise is introduced. The measured phase noise is (172dBc/Hz@10 kHz and the power dissipation is 0.36 mW at power supply 3V.     

5-GHz Low Power Current-Reused Balanced CMOS Differential Armstrong VCOs

This letter proposes 5-GHz low power differential Armstrong voltage controlled oscillators (VCOs) based on balanced topology. One designed VCO uses two single-ended Armstrong VCOs coupled to each other in parallel by balanced structure. The other current-reused VCO uses two single-ended Armstrong VCOs stacked in series. The former VCO oscillates from 4.96 to 5.34GHz and the power consumption is 3.9mW at 0.6-V supply voltage. The latter operates from 4.98 to 5.45GHz and dissipates 2.59mW at 1.8-V supply voltage. The measured phase noises are about -116.71dBc/Hz and -110.02dBc/Hz at 1-MHz offset frequency from 5.1-GHz band, respectively. The former and the latter VCO have an advantage of low power consumption and provide a good figure of merit of about -185dBc/Hz and -180dBc/Hz, respectively     

Low Phase-Noise and Low-Power CMOS VCO Constructed in Current-Reused Configuration

A Ku-band CMOS voltage-controlled oscillator (VCO) constructed in a modified current-reused configuration is presented in this letter. Two dc level shifters combined into two metal-insulator-metal capacitors are adopted to solve the transconductance and load mismatch problems of the conventional current-reused VCO for obtaining more symmetrical oscillation signals and lowering the phase noise of oscillator. A prototype was designed and measured to verify the design concept. The measurement results demonstrate the central oscillation signal of 16 GHz to be associated with the 900 MHz tuning range and -111 dBc/Hz phase noise at 1 MHz offset. The power consumption of the VCO core is only 8.1 mW. The measurement result evaluated by means of a figure of merit is about -186.8 dBc/Hz.     

一种5~6 GHz宽带全集成CMOS低噪声放大器

采用55 nm标准CMOS工艺,设计并流片实现了一种应用于Wi-Fi 6(5 GHz)频段的宽带全集成CMOS低噪声放大器(LNA)芯片,包括源极退化共源共栅放大器、负载Balun及增益切换单元。在该设计中,所有电感均为片上实现;采用Balun负载,实现信号的单端转差分输出;具备高低增益模式,以满足输入信号动态范围要求。测试结果表明,在高增益模式下该放大器的最大电压增益为20.2 dB,最小噪声系数为2.2 dB;在低增益模式下该放大器的最大电压增益为15 dB,最大输入1 dB压缩点为-3.2 dBm。芯片核心面积为0.28 mm²,静态功耗为10.2 mW。     

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode     

全集成CMOS SCA接收机单片化探讨

本文对调频副载波(SCA)广播接收机的单片化设计进行了探讨,提出了一种新的适合CMOS工艺的全集成SCA接收机结构。接收机采用Weaver-零中频结构实现下变频和二次解调功能,节省了片外镜像抑制滤波器,大大提高了接收机的集成度,降低了接收机的成本和功耗,显示了广阔的潜在应用前景。     

一个应用于探测生理信号SoC中的CMOS全集成高线性度低噪声上变频器设计

本文设计一款用于探测生理信号SoC芯片中的5GHz双边带上变频器.该混频器基于传统的吉尔伯特单元,采用交流耦合current-bleeding结构以及三阶非线性失真抵消技术抑制非线性.通过将跨导级晶体管偏置在不同的工作区域(transconductance-boost结构),使得带内变频损失小于5dB而IIP3介于22.3dBm到39.8dBm,而且双边带噪声指数小于8.2dB.应用全差分结构和感性源极钝化,再次抑制了二阶以及三阶失真.全部上变频器在1.2V供电条件下总功耗为8.4mW.     

用于无线局域网的CMOS射频前端发送器

介绍了一种用于802.11b无线局域网的高线性度射频前端发送器的设计与实现。该发送器采用直接转换结构,从而最大程度地减小了所需的片外和片上元件。电路采用0.18μmCMOS工艺实现。发送器包括两个低通滤波器、一个单边带混频器、一个功率预放大器和一个产生正交本振信号的除2分频器。发送器能够以3 dB一级提供12 dB的增益控制,输出1 dB压缩点为7.7 dBm,正常输出功率为2 dBm。整个发送器工作时消耗电流40 mA,工作电压1.8 V,芯片面积(不包括焊盘)为1.8 mm×1.5 mm。     

2.45 GHz全集成CMOS功率放大器设计

在一个RF收发机系统中,功率放大器的集成问题一直是难点之一.首先简要介绍开关模式功率放大器及其提高效率的理论基础,然后采用0.18 μm CMOS工艺给出了工作在2.45 GHz的全集成单片功率放大器的设计,并采用ADS仿真软件验证了设计的正确性.     

一种粒子探测器的CMOS读出电路设计

提出了新型的应用于粒子探测器CMOS读出电路中的电荷灵敏放大器和CR-(RC)n半高斯整形器的结构.电荷灵敏放大器采用多晶硅电阻做反馈来减小噪声,仿真发现与传统结构相比,在探测器电容高达150pF时,输入等效噪声电荷数由5036个电子减小到2381个,代价是输出摆幅减小了0.5V.在整形器中,MOS管电阻与多晶硅电阻串联,通过调节MOS管的栅压来改变阻值,以补偿工艺的偏差,在不明显降低线性度的情况下保证了时间常数能够比较精确控制.     

2.4GHz全集成CMOS Doherty功率放大器

采用0.18μm CMOS工艺设计并制作了一个2.4 GHz全集成CMOS Doherty功率放大器.着重考虑了片上螺旋电感的回流路径对电感模型的影响,并在设计中使用了一种新颖的螺旋电感版图结构来避免回流路径的影响.实测结果表明该功率放大器增益达到16dB,1dB压缩点为20.5dBm,峰值输出功率和对应功率附加效率分别为21.2dBm和20.4％,整个芯片面积为2.8mm×1.7mm.     

一种粒子探测器的CMOS读出电路设计

提出了新型的应用于粒子探测器CMOS读出电路中的电荷灵敏放大器和CR-(RC)n半高斯整形器的结构.电荷灵敏放大器采用多晶硅电阻做反馈来减小噪声,仿真发现与传统结构相比,在探测器电容高达150pF时,输入等效噪声电荷数由5036个电子减小到2381个,代价是输出摆幅减小了0.5V.在整形器中,MOS管电阻与多晶硅电阻串联,通过调节MOS管的栅压来改变阻值,以补偿工艺的偏差,在不明显降低线性度的情况下保证了时间常数能够比较精确控制.