硅尖的制备

隧道硅尖的制备是微机械隧道传感器制作的一个重要组成部分，通过对ICP刻蚀和湿法各向异性刻蚀工艺制备硅尖实验的研究，得到了合适的工艺条件以及较理想的硅尖。     

硅尖的制备

隧道硅尖的制备是微机械隧道传感器制作的一个重要组成部分 ,通过对ICP刻蚀和湿法各向异性刻蚀工艺制备硅尖实验的研究 ,得到了合适的工艺条件以及较理想的硅尖     

硅尖的制备

隧道硅尖的制备是微机械隧道传感器制作的一个重要组成部分,通过对ICP刻蚀和湿法各向异性刻蚀工艺制备硅尖实验的研究,得到了合适的工艺条件以及较理想的硅尖.     

场发射锥尖的制备及特性研究

研究了倒金字塔填充型锥尖及正向刻蚀硅尖的制备工艺,采用了两种封装结构测试了场发射硅尖阵列的发射特性,并分析比较了这两种结构的特点及用于制备高频微波器件的可能性。     

场发射锥尖的制备及特性研究

研究了倒金字塔填充型锥尖及正向刻蚀硅尖的制备工艺，采用了两种封装结构测试了场发射硅尖阵列的发射特性，并分析比较了这两种结构的特点及用于制备高频微波器件的可能性。     

各向异性腐蚀制备纳米硅尖

采用KOH溶液各向异性腐蚀单晶硅的方法制备高纵横比的纳米硅尖,研究了腐蚀溶液的浓度、添加剂异丙醇(IPA)对硅尖形状的影响。设计了硅尖制作的工艺流程,制备了形状不同、纵横比值为0.52～2.1的硅尖,并结合晶面相交模型,提出了硅尖晶面的判别方法,讨论了实验中出现的{411}和{331}晶面族两种硅尖晶面类型,实验结果和理论分析相一致。通过分析腐蚀溶液的质量分数和添加剂对{411}、{331}晶面族腐蚀速度的影响,得到了制备高纵横比纳米硅尖的工艺参数。实验结果表明:当正方形掩模边缘沿<110>晶向时,在78℃、质量分数40的KOH溶液中腐蚀硅尖,再经980℃干氧氧化3h进行锐化削尖,可制备出纵横比大于2、曲率半径达纳米量级的硅尖阵列。     

硅尖阵列二极管温度性能的研究

简述了真空微二极管的结构参数设计、工作特点、工艺制备技术。给出了微二极管不同的温度下Ｆ－Ｎ曲线及湿法化学腐蚀制备硅尖的形貌。该微二极管起始电压为２Ｖ左右，发射尖电流５μＡ／锥尖。     

硅尖阵列二极管性能的研究

简述了真空微二极管的结构参数设计考虑、工作特点、工艺制备技术。给出了微二极管不同温度下的Ｆ－Ｎ曲线及湿法腐蚀制备硅尖的开貌。该微二极管转换电压为２伏左右，发射锥尖电流为５μＡ／锥尖。     

用硅的各向异性腐蚀工艺制备发射硅尖阵列

本文介绍了真空微电子器件场发射阴极硅尖阵列的制备工艺技术。采用硅的各向异性腐蚀工艺和氧化削尖技术制成了形状和发射性能均较好的硅尖阵列，测试结果表明，起始发射电压为５～６Ｖ，发射电流在阳极电压为２０Ｖ时为０．５ｍＡ，反向击穿电压为７５Ｖ。     

硅尖阵列场致发射微二极管的制备及特性研究

本文采用各向异性腐蚀和干－湿－干氧化锐化工艺，在ｎ型，（１００）晶向、电阻率为３～５Ωｃｍ、３英寸硅片上均匀制备了三种结构硅尖阵列场致发射二极管。锥尖密度达１５０００个／ｍｍ￣２，硅尖曲率半径小于３０ｎｍ；在３５Ｖ收集极电压下，单尖发出电流达０．１４μＡ，其Ⅰ—Ⅴ曲线与Ｆ—Ｎ公式类似。     

Gold-coated scanning probes for direct `write`of sub-micron metallic structures

The fabrication and application of new gold-coated scanning probes (SPs) for direct `write? of submicron metallic structures are reported. The SP consists of a base structure made of silicon nitride and a thin gold coating. The tip profile and radius of curvature are tightly controlled in the probe fabrication to ensure a predictable tip?substrate contact. By scanning a fabricated probe on a single crystal silicon surface in an ambient environment, sub-micron gold lines were formed as a result of direct gold material transfer from the SP tip onto the silicon surface, which is believed to be induced by the friction and wear associated with the probe scanning.     

系统集成中的高阻硅IPD技术

集成无源器件(IPD)技术可以将分立的无源器件集成在衬底内部,提高器件Q值及系统集成度。由于高阻硅衬底具有良好的射频特性,高阻硅IPD技术可以制备出Q值高达70以上的电感。高阻硅IPD基于薄膜技术具有高精度、高集成度等特点,可将无源器件特征尺寸缩小一个数量级。同时可利用成熟的硅工艺平台,便于批量生产降低成本。此外,高阻硅IPD技术可与硅通孔(TSV)技术兼容,可实现三维叠层封装。分析表明,高阻硅IPD技术在系统集成中具有广泛应用前景。     

The silicon PCB

In its simplest form, a silicon hybrid is essentially a miniaturised PCB built on a silicon wafer, and like any other PCB it is made up of layers of metal tracks separated by a suitable dielectric. However, unlike a conventional PCB, a silicon hybrid is manufactured using IC fabrication techniques. The author discusses the Research Initiative in Silicon Hybrids (RISH). Developing silicon hybrids as a viable interconnection technology requires the successful solution of a wide range of problems. There is the obvious issue of developing reliable manufacturing techniques, but silicon hybrids also create their own special demands on chip-to-substrate connection technology, packaging, substrate and IC testing, and computer-aided-design (CAD) software. All these different aspects of silicon-hybrid development are being covered by the RISH project with a view to providing the collaborating companies with a `tool-box' of processes from which the appropriate tool can be selected for a given application     

提高抗激光烧蚀能力的表面尖形微结构器件

讨论了光刻热熔成形工艺灰度掩模技术结合离子束蚀刻制作面阵尖形微结构器件的问题,分析了几种凸尖及凹尖结构抗烧蚀的能力强于平面端面同质器件的原因,所作的若干分析结果可用于这类器件的实际制作的应用。     

Anodic bonding of glass and silicon wafers with an intermediate silicon nitride film and its application to batch fabrication of SPM tip arrays

This paper reports a detailed study of wafer-level anodic bonding with a dielectric intermediate layer and its application to the fabrication of scanning probe microscope (SPM) probe arrays. First, the bonding performance between sodium-ion rich glass and silicon nitride coated silicon substrate is characterized. The effects of voltage, tool pressure, bonding time, surface properties, and cleanliness are thoroughly studied. Then, the silicon nitride based SPM probe arrays consisted of pyramidal tip and 1.5 μm-thickness cantilever are successful bonded and transferred to Pyrex 7740 glass substrate by use of our optimized wafer-scale electrostatic force bonding condition. The nano-imaging capability of the scanning probe array is also demonstrated.     

Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication

This paper provides a detailed overview of silicon carrier-based packaging for 3-D system in packaging application. In this work the various critical process modules that play a vital role in the integration and fabrication of silicon carrier with high aspect ratio tapered through-silicon interconnections have been explained and discussed with experimental data. A method of fabricating tapered deep silicon via in a three-step approach has been developed and characterized which controls via depth, sidewall profile, and surface roughness effectively. A low-temperature dielectric deposition process is also developed that has minimum residual stress and good dielectric coverage on the via sidewall. The above processes were then integrated with back-end processes like seed metallization, copper electroplating, chemical mechanical polishing, and wafer thinning to realize a fully integrated silicon carrier fabrication technology. The silicon carriers were finally assembled and tested for through silicon interconnection.      

Application of selective silicon epitaxial growth for CMOS technology

The application of selective silicon epitaxial growth for device isolation is described. An improved selective epitaxial isolation technology is presented in the fabrication of CMOS LSI. This advanced process technology results from a superior selectivity for selective silicon deposition. A CMOS ring oscillator with a twin-well structure is fabricated by using this selective epitaxial isolation technology. The feasibility of using an oversized contact, due to the nature of its steeper oxide-to-silicon isolation boundary, is demonstrated.     

The HARPSS process for fabrication of precision MEMS inertial sensors

The high aspect-ratio combined poly- and single-crystal silicon micromachining technology (HARPSS) and its application to fabrication of precision MEMS inertial sensors are presented. HARPSS is a single wafer, all silicon, front-side release process which is capable of producing 10–100's of microns thick, electrically isolated, 3-D poly- and single-crystalline silicon microstructures with various size air-gaps ranging from sub-micron to tens of microns. High aspect-ratio (>50:1) polysilicon structures are created by refilling 100's of microns deep trenches with polysilicon deposited over a sacrificial oxide layer. This technology provides features required for precision micromachined inertial sensors. The all-silicon feature of this technology improves long term stability and temperature sensitivity while fabrication of large area, vertical electrodes with sub-micron gap spacing will increase the sensitivity by orders of magnitude.     

Polysilicon thin-film transistors on polymer substrates

Different approaches to fabricate low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) on polymer substrates are reviewed and the two main routes are discussed: (1) standard fabrication of LTPS TFTs on glass substrates followed by a transfer process of the devices on the polymeric substrate; (2) direct fabrication of the devices on the polymeric substrate. Among the different techniques we have described in more detail the process we have recently developed for the fabrication of LTPS TFTs directly on ultra-thin polyimide (PI) substrate. LTPS TFT technology is particularly suited for high performance flexible electronics applications, due to the excellent device characteristics, good electrical stability and CMOS technology. Flexible display application remains the most attractive application for LTPS technology, especially for AMOLED displays, where device stability and the possibility to integrate the driving circuits make LTPS technology superior to all the other competitive TFT technologies. Among the other applications, particularly promising is also the application to flexible smart sensors, where integration of a front-end electronics is essential. Some examples of flexible gas sensors and pressure sensors, integrated with simple readout electronics based on LTPS TFTs and fabricated on ultra-thin PI substrate, are presented.