Mechanical fatigue test method for chip/underfill delamination in flip-chip packages

Underfill resin between Si chips and printed circuit boards is useful for improving the reliability of flip-chip packages. Generally, thermal cycle tests (TCTs) are applied to electronic packages under development in order to prove their reliability. At the early stage of development, however, a more effective test method is desirable, because TCTs are time-consuming. A new mechanical fatigue test for the underfill resin in flip-chip packages, namely the four points support test method, is proposed in this paper. The validity of the mechanical test method could be verified from the results of stress analyses and experiments. Considering the chip/underfill delamination statistically based on the assumption of Markov process, it was shown that the delamination probability during cyclic loads could be estimated with equations of the displacement range and number of cycles.     

电阻法测量无铅焊点蠕变的有效性实验研究

为了解用于焊点性能评估的电阻测试法能否精确反映其蠕变特性,利用特制的焊点测试系统,同步采集无铅焊点在室温、25 N载荷下的电阻应变和剪切蠕变.实验表明它们的总体变化趋势相似,均可分为线性与指数阶段,但变化速率存在明显差异.两者临界拐点的延时程度与焊点的尺寸因子k有关,在一定的范围内(k= 4.5～8.5),延时程度仅在...     

Observations of microstructural coarsening in micro flip-chip solder joints

Coarsening of solder microstructures dramatically affects fatigue lifetimes. This paper presents a study of microstructural evolution due to thermal cycling and aging of small solder joints. The lead-tin solder joints in this study have a height of 55 5 m and a tin content of 65–70 wt.%, with a degenerate eutectic microstructure. The joint microstructure coarsens more rapidly during aging at 160°C than cycling from 0–160°C. No coarsened bands are observed. The cycling data scales with standard coarsening equations, while the aging data fits to an enhanced trend. The joints experiencing 2.8% strain during cycling fail by 1000 cycles.     

Mechanical response of solder joints in flip-chip type structures

The mechanical response of PbSn solder joints of two different solder alloys (37 wt.% Pb - 63 wt.% Sn and 95 wt.% Pb - 5 wt.% Sn) used as flip-chip type interconnects is measured through mechanical testing (in tension and in shear). The influence of solder pad composition (Au and Ni) upon the behaviour of the solder joints is examined. Fatigue testing performed upon flipchip samples demonstrates the difference in mechanical comportment between Pb37Sn63 and Pb95Sn5 solders. A model for predicting fatigue life is put forward.     

Investigation on flip chip solder joint fatigue with cure-dependent underfill properties

A cure-dependent viscoelastic constitutive relation is applied to describe the curing process of epoxy underfill in flip chip on board (FCOB). The chemical shrinkage of the epoxy underfill during the curing process is applied via incremental initial strains. Thus, the stress and strain build-up, caused by the simultaneous increase in stiffness and shrinkage during the curing process, are simulated. Accelerated fatigue experiments with thermal cycles from -55/spl deg/C to 80/spl deg/C are carried out for a specially designed flip chip configuration. Based on the obtained curing induced initial stress and strain fields, thermo-mechanical predictions are presented for the test carriers. The solder bumps are modeled with temperature dependent visco-plastic properties. A combination of a Coffin-Manson based fatigue relation and a creep fatigue model is used as fatigue failure criterion. The results show that the finite element method (FEM)-based fatigue life predictions match better with the experimental results, if the curing induced initial stress state is taken into account. The effect of cure-induced hydrostatic stress is qualitatively investigated by using a modified energy partitioning damage model with a correction factor in the creep damage formulation to take into account the effect of the hydrostatic stress.     

Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages

Detailed three-dimensional finite element analysis was carried out for area-array solder-bumped flip-chip packages. The analysis enabled determinations of accurate three-dimensional effects on stress distributions as well as local fracture behaviors under thermal load. The 3D analysis also estimated thermal fatigue life of solder bumps. Since dimensions of various components span more than three orders of magnitude, the multi-scale finite element models were utilized to elucidate detailed deformation state near solder bumps. The global–local approach identified of critical solder bumps due to the overall deformation and investigated of interfacial delamination at microstructural level. The local model contained a single solder bump and sub-micron UBM layers. The two-step modeling approach enabled accurate fracture analysis otherwise difficult in large 3D models. Our analysis found the crack driving force and preferred delamination direction based on the 3D J-integral calculations. Shear deformations within and surrounding solder bump connectors were also investigated. The results revealed higher deformation in the 3D model than those predicted from 2D models. Additionally, the strain components were different. This has an important implication on the plastic flow characteristics during cyclic loading. Our model estimated about 25% greater steady-state shear strains in the 3D model than those in the 2D models. This result suggests a much shorter fatigue life than that based on the 2D analysis.     

Temperature and current-density distributions in flip-chip solder joints with Cu traces

Three-dimensional simulation was performed to investigate the temperature and current density distribution in flip-chip solder joints with Cu traces during current stressing. It was found that the Cu traces can reduce the Joule heating effect significantly at high stressing currents. When the solder joints were stressed by 0.6 A, the average temperature increases in solder bumps with the Al traces was 26.7°C, and it was deceased to 18.7°C for the solder joint with the Cu traces. Hot spots exist in the solder near the entrance points of the Al or Cu traces. The temperature increases in the hot spot were 29.3°C and 20.6°C, for solder joints with the Al traces and Cu traces, respectively. As for current density distribution, the maximum current density inside the solder decreased slightly from 1.66×10⁵ A/cm² to 1.46×10⁵ A/cm² when the Al traces were replaced by the Cu traces. The solder joints with the Cu traces exhibited lower Joule heating and current crowding effects than those with the Al traces, which was mainly attributed to the lower electrical conductivity of the Cu traces. Therefore, the solder joints with the Cu traces are expected to have better electromigration resistance.     

Impact of temperature cycle profile on fatigue life of solder joints

In this paper the influence of the temperature cycle time history profile on the fatigue life of ball grid array (BGA) solder joints is studied. Temperature time history in a Pentium processor laptop computer was measured for a three-month period by means of thermocouples placed inside the computer. In addition, Pentium BGA packages were subjected to industry standard temperature cycles and also to in-situ measured temperature cycle profiles. Inelastic strain accumulation in each solder joint during thermal cycling was measured by high sensitivity Moire interferometry technique. Results indicate that fatigue life of the solder joint is not independent of the temperature cycle profile used. Industry standard temperature cycle profile leads to conservative fatigue life observations by underestimating the actual number of cycles to failure.     

Geometrical effect of bump resistance for flip-chip solder joints: Finite-element modeling and experimental results

The bump resistance of flip-chip solder joints was measured experimentally and analyzed by the finite-element method. Kelvin structures for flip-chip solder joints were designed and fabricated to measure the bump resistance. The measured value was only about 0.9 mΘ at room temperature, which was much lower than that expected. Three-dimensional (3-D) modeling was performed to examine the current and voltage distribution in the joint. The simulated value was 7.7 mΘ, which was about 9 times larger than the experimental value. The current crowding effect was found to be responsible for the difference in bump resistance. Therefore, the measured bump resistance strongly depended on the layout of the Kelvin structure. Various layouts were simulated to investigate the geometrical effect of bump resistance, and a significant geometrical effect was found. A proper layout was proposed to measure the bump resistance correctly. The Kelvin structure would play an important role in monitoring void formation and microstructure changes during the electromigration of flip-chip solder joints.     

Underfill constraint effects during thermomechanical cycling of flip-chip solder joints

The presence of an “underfill” encapsulant between a microelectronic device and the underlying substrate is known to substantially improve the thermal fatigue life of flip-chip (FC) solder joints, primarily due to load-transfer from the solder to the encapsulant. In this study, a new single joint-shear (SJS) test, which allows the measurement of the strain response of an individual solder ball during thermomechanical cycling (TMC), has been used to investigate the impact of the constraint imposed by the underfill on a solder joint. Finite element (FE) modeling has been used to demonstrate that the SJS sample geometry captures most of the deformation characteristics of an FC joint and to provide insight into experimental observations. It has been shown that the strain response of a eutectic Pb-Sn solder joint is influenced significantly by in-situ microstructural coarsening during TMC, which in turn is dependent on the underfill properties. In general, underfill properties, which allow the imposition of large compressive-hydrostatic stresses on the solder joint, were the most effective in reducing coarsening. Phase coarsening prevented the stabilization of the stress-strain response of the solder, even in the absence of crack damage, and was found to depend strongly on the local inelastic-strain state within the joint. This necessitates that future solder deformation models account for strain-history-dependent microstructural evolution and that underfill properties be optimized to minimize the extent of coarsening during TMC in order to maximize joint life.     

Superplastic creep of eutectic tinlead solder joints

This paper presents experimental evidence that as-solidified eutectic Pb-Sn solder joints can exhibit superplastic behavior in shear creep loading. Stepped load creep tests of as-solidified joints show a change in the stress exponent from a high value typical of con-ventional creep at high stress and strain rate to a superplastic value near 2 at lower stress and strain rates. In addition, the change in stress exponent is accompanied by a change in the activation energy for creep from a value near that for bulk self-diffusion (20 kcal/mol) to a value near that for grain boundary diffusion (12 kcal/mol). The total shear deformation of joints in stress-rupture tests performed at 65° C are found to ex-ceed 150%. The concomitant observation that quenched solder joints creep faster than air-cooled ones is attributed to a grain, or phase, size dependence of the strain rate. The source of superplastic behavior is a fine, equiaxed microstructure. It is not yet clear whether the superplastic microstructure is present in the as-solidified joint, or develops during the early stages of plastic deformation.     

不同冷却速度对SMT焊点热循环寿命的影响

采用水冷、空冷和炉冷的不同冷却方式，对焊点的热循环寿命进行了初步研究，结果表明，对ＳｎＰｂ６０／４０钎料，空冷焊点的热循环寿命最高，水冷的最差。焊点的断面均是沿晶和穿晶的混合断口，并伴有疲劳辉纹，呈现蠕变和疲劳交互作用的断裂特征。     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Effect of polyimide baking on bump resistance in flip-chip solder joints

The effect of polyimide (PI) thermal process on the bump resistance of flip-chip solder joint is investigated for 28 nm technology device with aggressive extreme low-k (ELK) dielectric film scheme and lead-free solder. Kelvin structure is designed in the bump array to measure the resistance of single solder bump. An additional low-temperature pre-baking before standard PI curing increases the bump resistance from 9.3 mΩ to 225 mΩ. The bump resistance increment is well explained by a PI outgassing model established based on the results of Gas Chromatography–Mass Spectrophotometer (GC–MS) analysis. The PI outgassing substances re-deposit on the Al bump pad, increasing the resistance of interface between under-bump metallurgy (UBM) and underneath Al pad. The resistance of interface is twenty-times higher than pure solder bump, which dominates the measured value of bump resistance. Low-temperature plasma etching prior to UBM deposition is proposed to retard the PI outgassing, and it effectively reduces the bump resistance from 225 mΩ to 10.8 mΩ.     

Cross-interaction of under-bump metallurgy and surface finish in flip-chip solder joints

The cross-interaction of the under-bump metallurgy (UBM)/solder interface and the solder/surface-finish interface in flip-chip solder joints was investigated. In this study, the UBM on the chip side was a single layer of Cu (8.5 μm), and the surface finish on the substrate side was a 0.2-μm Au layer over 5-μm Ni. It was shown that, after two reflows, the Ni layer of the surface finish had been covered with (Cu_1−xNi_x)₆Sn₅. This shows that the effect of cross-interaction of the two interfaces is important even during the reflow stage. During subsequent solid-state aging at 115°C, 135°C, and 155°C, the formation of (Cu_1−xNi_x)₆Sn₅ over the Ni layer was found to have the effect of reducing the Ni consumption rate. At the same time, the Cu consumption rate of the UBM was accelerated. The results of this study show that the selection of the UBM and the surface finish has to be considered together because the cross-interaction of the two interfaces plays an important role.     

Effect of underfill filler settling on thermo-mechanical fatigue analysis of flip-chip eutectic solders

Underfills containing filler particles exhibit filler settling during the (capillary-based) wicking and curing processes, thus causing the reliability estimation to deviate from that of the presumed base of no filler settling. This paper examines the thermo-mechanical responses of the solder joints in flip-chip packaging to various conditions of filler settling. We built five y-dependent profiles for describing the uniform, bilayered, and gradual settling of filler spheres in the through-depth direction of the underfill and used the Mori-Tanaka method to calculate the effective material properties of the filler-resin underfill compound by considering a linearly elastic, temperature-dependent resin with a glass transition temperature range of 70-130 °C. For each settling profile we analyzed the fatigue indicators, referred to as the inelastic shear strain ranges and the inelastic shear strain energy densities of the solder joints, and compared their magnitudes against the extent of filler settling. The results show that the fatigue indicators depend on the extent of filler settling. A greater extent of bilayered filler settling produced larger (in magnitude) fatigue indicators. The fatigue indicators associated with gradual filler settling, however, were almost always smaller, on average, than those associated with no filler settling, indicating that some types of filler settling might favor a longer solder fatigue life. This preliminary but intriguing finding may be partially explained by considering the asymmetric thermal mismatch in the through-depth direction of the underfill; a comparatively good thermal match near the bottom side of the solder joints may compensate for the thermal mismatch at the top side, thus contributing to an overall better thermal match in the solder joint.     

The creep behavior of In-Ag eutectic solder joints

The addition of 3 wt.% Ag to In results in a eutectic composition with improved mechanical properties while only slightly lowering the melting temperature. Steady-state creep properties of In-Ag eutectic solder joints have been measured using constant load tests at 0, 30, 60, and 90°C. Constitutive equations are derived to describe the creep behavior. The data are well represented by an equation of the form proposed by Dorn: a power-law equation applies to each independent creep mechanism. Two parallel mechanisms were observed for the In-Ag eutectic joints. The high-stress mechanism is a bulk mechanism with a thermal dependence dominated by the thermal dependence of creep in the Inrich matrix. The low-stress mechanism is a grain boundary mechanism. Results of this work are discussed with regard to creep behavior of typical eutectic systems.     

Superplastic creep of low melting point solder joints

In prior work, we showed that eutectic Sn-Pb solder joints exhibit superplastic behavior after rapid solidification. Further examples of superplasticity in nominally air-cooled solder joints are reported in this study of three low-melting point alloys: 40In-40Sn-20Pb (wt. %), eutectic 52In-48Sn, and 43Sn-43Pb-14Bi, which were creep-tested in shear at 20°, 65°, and 90° C. The test results indicate that above 65° C, the indium-containing solders have stress exponents between 2.4 to 2.9, a possible overall shear strains of 500%, and an absence of primary creep; at 90° C, 43Sn-43Pb-14Bi solder has a stress exponent close to 2.3. Optical microstructures of the three solders are presented; they help to explain the superplastic behavior.     

Low-cycle fatigue characteristics of Sn-based solder joints

Low-cycle, lap-shear fatigue behavior of Sn-based, Pb-free solder alloys, Sn-3.5Ag, Sn-3.5Ag-Cu, Sn-3.5Ag-Bi, and Sn-0.7Cu, were studied at room temperature using specimens with printed circuit board (PCB)/solder/PCB structure under total displacement of ±10 μm, 12 μm, 15 μm, and 20 μm. The fatigue lives of various solder joint materials, defined as 50% load drop, were correlated with the fracture paths and analyzed using the Coffin-Manson relation, Morrow’s plastic-energy dissipation model, and Solomon’s load-drop parameter. The Sn-3.5Ag, Sn-0.7Cu eutectics, and Sn-3.5Ag-Cu ternary alloys showed the same level of fatigue resistance, while Bi-containing alloys showed substantially worse fatigue properties. Cross-sectional fractography revealed cracks initiated at the solder wedge near the solder mask and subsequently propagated into the solder matrix in the former group of alloys, in contrast with the crack propagation along the solder/under bump metallurgy (UBM) interfaces in the Sn-3.5Ag-Bi alloys. Inferior fatigue resistance of Bi-containing alloys was ascribed to high matrix hardness, high stiffness, possible Bi segregation to the interface, and high residual stress in the interfacial area.