An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Characterization of oxide traps in 0.15 μm MOSFETs using random telegraph signals

Random telegraph signals (RTS) have been used to characterize oxide traps of W×L=0.97×0.15 μm² medium-doped drain n-MOSFETs. RTS have been measured in the linear and saturation regions of operation, both in forward and reverse modes where the drain and source are reversed. The contribution of mobility fluctuations as well as number fluctuations to the amplitude of RTS has been investigated. The scattering coefficient due to screened Coulomb scattering effect is computed from the measured data as a function of channel carrier density. The depth of the position of the trap in the oxide from Si–SiO₂ interface is calculated utilizing the dependence of the emission and capture times on the gate voltage. In addition, the position of the trap along the channel with respect to the source is obtained using the difference in the drain voltage dependence of the capture and emission times between the forward and reverse modes. Knowing the location of the trap in the oxide and along the channel, the energy associated with the trap can be extracted accurately from the data. This technique allows one to evaluate the trap energy at the point where the trap is located without any assumptions about the location of the trap or the need for variable temperature measurements. The probed trap was found to be an acceptor type center (repulsive for an n-MOSFET) located at about 27 Å deep the oxide, half-way between drain and source with an energy of E_Cox−E_T=3.04 eV, slightly above the conduction band edge.     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

Bias stress effect in solution-processed organic thin-film transistors: Evidence of field-induced emission from interfacial ions

Though bias-stress instability in organic thin film transistors (OTFTs) has been studied in a variety of architectures, it is as yet poorly understood. We have investigated the bias-stress effect in fully solution-processed TIPS-pentacene based OTFTs with polymer dielectric by applying prolonged gate-source voltage (V_GS). The interface is deliberately defect engineered to obtain excellent adhesion and reasonably good steady state characteristics. Both increasing and decreasing behavior of drain-source current (I_DS) drift over 3000s have been observed, and analyzed in terms of electron capture and emission respectively. The step-by-step change in V_GS is compared with the one step change from V_GS = 0V to V_GS = −40V. It has been observed that, for the case of step-wise increase in gate bias, the I_DS transients are slower by many orders of magnitude than if the V_GS is directly switched to deep bias (−40V) in a single step. A phenomenological model is used to explain the I_DS decaying transients. The field induced emission of carriers from interfacial traps is shown to be central to the model and experimental features. The effect due to a prolonged application of drain-source voltage (V_DS) is small, though noticeable in terms of increasing the I_DS only by 3% with continuous application of V_DS for 3000 s.     

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V_GS=0 V and V_GS=V_DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current (I_Gmax). In the case of V_GS corresponding to I_Gmax two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V_GS=V_GS@I_Gmax to V_GS=V_DS.     

Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO₂ gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, ΔV_TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO₂ interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO₂ interface (P_b centers) and its vicinity (E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I_D − V_G (ΔV_TH) techniques, however, suggests that ΔV_TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO₂/SiO₂ gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO₂ and high-k gate stacks suggesting a common mechanism of the interface degradation.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing

Electrical characterization of the hafnium oxide (HfO₂) gate dielectric films prepared by Hf sputtering in oxygen was conducted. By measuring the current–voltage (I–V) characteristics at temperature ranging from 300 to 500 K, several abnormalities in the I–V characteristics are recorded. For temperatures below 400 K, the current–voltage characteristics in high field region can be plotted with the Fowler–Nordheim law but a stronger temperature dependence was observed. Large flatband voltage shifts in the Al/HfO₂/Si capacitor were observed. The capacitance–voltage characteristics and flatband shifts are found to depend strongly on the post-deposition annealing temperature and duration. To study the reliability against high electric field, constant voltage stressing on the samples was conducted. We found that the trap energy levels are shallow and the oxide traps can be readily filled and detrapped at a low bias voltage.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.     

High air stability of threshold voltage on gate bias stress in pentacene TFTs with a hydroxyl-free and amorphous fluoropolymer as gate insulators

We investigated the air stabilities of threshold voltages (V_th) on gate bias stress in pentacene thin-film transistors (TFTs) with a hydroxyl-free and amorphous fluoropolymer as gate insulators. The 40-nm-thick thin films of spin-coated fluoropolymer had excellent electrical insulating properties, and the pentacene TFTs exhibited negligible current hysteresis, low leakage current, a field-effect mobility of 0.45 cm²/Vs and an on/off current ratio of 3 × 10⁷ when it was operated at −20 V in ambient air. After a gate bias stress of 10⁴ s, a small V_th shift below 1.1 V was obtained despite non-passivation of the pentacene layer. We have discussed that the excellent air stability of V_th was attributed to the insulator surface without hydroxyl groups.     

MOSFET中大幅度随机电报信号噪声的动力学特性

对 MOSFET器件的随机电报信号噪声 ( RTS)的特征进行了研究。室温下在极细沟道样品中观测到了大幅度 (大于 60 % )的 RTS,通过测量 RTS的俘获时间和发射时间与栅压和温度的依赖关系 ,获得了氧化层陷阱的位置与能级 ,证实了氧化层陷阱的热激活模型在细沟道 n MOSFET中仍然成立。同时发现当器件工作在弱反型区时 ,RTS幅度基本与栅压无关。对 RTS的动力学机制的分析及数值模拟表明 ,当沟道宽度减小至 4 0 nm以下时 ,由荷电陷阱对沟道载流子散射而产生的迁移率涨落对 RTS的幅度的影响起主导作用。     

The effect of oxygen in Ru gate electrode on effective work function of Ru/HfO2 stack structure

Effective work function (φ_m,eff) values of Ru gate electrode on SiO₂ and HfO₂ MOS capacitors were carefully examined and discussed from the viewpoint of an effect of oxygen incorporation in Ru gate electrode on φ_m,eff. Annealing at 400 °C in the reduction (3%H₂) and the oxidation (1%O₂) ambient resulted in similar changes in the φ_m,eff of Ru/HfO₂/SiO₂ and Ru/SiO₂ MOS capacitors. Furthermore, the Ru gate MOS capacitor after annealing in the oxidation condition have shown almost the same φ_m,eff value to that of RuO₂ gate MOS capacitors. The oxygen concentration in the Ru/HfO₂ interface after annealing in oxidizing atmosphere is approximately one order of magnitude higher than that after annealing in reducing atmosphere as confirmed by secondary ion mass spectroscopy analysis. Furthermore, the higher oxygen concentration at the Ru/dielectric interface leads to the higher φ_m,eff value, regardless of SiO₂ or HfO₂ dielectrics. This indicates that φ_m,eff of Ru gate MOS capacitor is dominantly determined by the oxygen concentration at the Ru/dielectric layer interface rather than the dipoles originated from the oxygen vacancy in HfO₂.     

A percolation study of RTS noise amplitudes in nano-MOSFETs by Monte Carlo simulation

A high efficiency 2D percolation model of RTS amplitudes in nanoscale MOSFETs based on the numerical results of potential and carriers density distributions in the channel obtained by solutions of coupled 2D Schrodinger and Poisson equations was presented. Using this model the dependences of relative RTS amplitudes ΔI_D/I_D on device geometry L_eff × W_eff, t_ox bias conditions I_D, V_G and trap locations along the channel were simulated and analyzed for a set of square n-MOSFETs. The results show reasonable agreement with published numerical or experimental data.     

Comparative studies of Pt and Ir schottky contacts on undoped Al0.36Ga0.64N

Schottky contacts of Pt and Ir on undoped Al_0.36Ga_0.64N have been fabricated and the ideality factor, the built-in voltage and the reverse bias current were determined using current–voltage measurements to make a comparison.The smallest ideality factors, the lowest reverse bias current and the highest built-in voltages have been obtained for Ir Schottky contacts.We have studied the effect of an annealing for Pt and Ir Schottky contacts, on the ideality factor, the built-in voltage and the reverse bias current. A decrease of the ideality factor and the reverse bias current associated to an increase of the built-in voltage have been obtained except for high annealing temperature (T > 400 °C).Reductions of 37% and 43% of the ideality factor and improvements of 24% and 41% of the built-in voltage have been obtained for Pt and Ir Schottky contacts, respectively, after an annealing performed at 350 °C during 30 min.Two different electrical stresses have also been applied on the ohmic and Schottky contacts during 164 h to study the reliability of the employed technology. In a first time, the devices have been stressed with a drain-to-source voltage V_DS of 20 V and a gate-to-source voltage V_GS of −5 V to submit the devices to an electrical field only and not to a thermal effect induced by the electrical current. In a second time, the aging stress has been applied for a V_DS of 20 V and for a V_GS of 0 V in order to study the impact of the electrical field and the thermal effect induced by the drain current on the electrical behaviours of Al_0.36Ga_0.64N/GaN transistors. This study has also shown the existence of electrical traps in the device structure and proved the good reliability of the involved technology.These comparative studies demonstrate that Ir is a better candidate than Pt for the realisation of Schottky contacts on undoped Al_0.36Ga_0.64N.     

Degradation of n-channel a-Si:H/nc-Si:H bilayer thin-film transistors under DC electrical stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN_x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress (V_G = 25 V, V_D = 0), (ii) on-state bias stress (V_G = 25 V, V_D = 20 V) and (iii) off-state bias stress (V_G = −25 V, V_D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.     

Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs

The hysteresis effect between forward and reverse drain-source voltage (V_DS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (V_TH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (V_DS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high V_DS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.