Process and device optimization of an analog complementary bipolarIC technology with 5.5-GHz fT pnp transistors

An analog complementary bipolar IC process has been developed featuring 9.0-GHz f_T npn and 5.5-GHz f_T pnp transistors. Process conditions for emitter, base, and collector of pnp transistors are optimized in order to achieve the best performance tradeoff between current gain, Early voltage, and cutoff frequency. With the optimized process conditions, the H_FE×V_A of pnp transistors is 350 V with f_T of 5.5 GHz and f_max of 8.5 GHz. These high performance pnp transistors have been integrated into an existing 9.0-GHz f_T npn bipolar process without introducing excessive additional process complexity and manufacturing costs. In addition, Schottky diodes, p-channel junction FET's and laser wafer trimmable precision NiCr resistors have been integrated into the process to enhance analog circuit design capability     

Modeling of current transport and 1/f noise in heterojunction bipolar transistors

An analytic model is proposed to determine the effect of band offsets at heteroemitter interface on the current transport and 1/f noise in heterojunction bipolar transistors (HBTs). The proposed model uses the modified form of drift-diffusion formalism, which requires that the net recombination rates be proportional to the densities of other type carriers across the heterointerface. The numerical analysis of the current–voltage and 1/f noise characteristics of Npn AlGaAs/GaAs HBT and npn GaAs BJT demonstrates that the role of band offsets at heteroemitter interface in the overall current transport and 1/f noise is very important in HBTs at low forward biases. The junction resistance due to diffusing minority electrons is much stronger (weaker) at small (high) forward biases than that due to recombined electrons and holes across the heteroemitted space charge region in both Npn AlGaAs/GaAs HBTs and npn GaAs BJTs.     

Measurements of 1/f noise amplitude modulated by a large-signal carrier in bipolar junction transistors

A novel experimental system for the investigation of frequency-translated flicker noise in bipolar junction transistors is demonstrated. First, transistors are characterized for their base–emitter junction behavior and flicker noise parameters in steady state. Then, measurements of the frequency conversion of 1/f noise are performed by the application of a large sinusoidal signal to the base–emitter junctions of bipolar junction transistors. The applied signal is varied in frequency and amplitude, and the resulting conversion gains are reported. A novel measurement technique, which enables the detection of noise fluctuations near a much larger signal is demonstrated. These results are compared with harmonic balance simulation.     

Simulation of npn and pnp AlGaN/GaN heterojunction bipolartransistors performances: limiting factors and optimum design

The performance capabilities of npn and pnp AlGaN/GaN heterojunction bipolar transistors have been investigated by using a drift-diffusion transport model. Numerical results have been employed to study the effect of the p-type Mg doping and its incomplete ionization on device performance. The high base resistance induced by the deep acceptor level is found to be one of the causes of limited current gain values for npn devices. Reasonable improvements of the dc current gain β are observed by realistically reducing the base thickness and consequently the transit time, in accordance with processing limitations. Base transport enhancement is predicted by the introduction of a quasi-electric field in the base. The impact of the base resistivity on high-frequency characteristics is investigated for npn AlGaN/GaN devices. Simulation results reveal the difficulty to achieve decent current gain values at high current density for pnp HBTs in common emitter configuration. Despite the high electron mobility in the n-type base that aids in reducing the base resistance, a preliminary analysis for pnp devices indicates limited rf performances caused by the reduced minority hole transport across the base     

Comparison of low frequency noise and high frequency performances of double and simple polysilicon Bi-CMOS BJT

The issue of this paper concerns 0.35 μm Bi-CMOS double polysilicon bipolar transistors and 0.5 μm Bi-CMOS simple polysilicon bipolar transistors. Low-frequency noise measurements are performed. Noise spectral densities are analysed versus bias and geometry. From these noise measurements, base and emitter series resistances are extracted. A comparison of both technologies is done. Though double polysilicon transistors have a more complex structure than the simple polysilicon ones, they exhibit similar or even better performances. Indeed, DC characteristics and noise levels are equivalent for both technologies. Double polysilicon transistors exhibit a reduction of the base resistance and a significant improvement of the transition frequency f_T is obtained.     

Scaling in npn and pnp heterostructure bipolar transistors

Calculating the cutoff frequency f_T of bipolar transistors from the emitter-to-collector delay neglects the heavy influence of parasitic reactances on the frequency response of realistic transistors. A more complete equivalent circuit modelling reveals that the speed advantage of npn against pnp heterojunction bipolar transistors of common geometry, base width, and doping profile decreases as the transistor is scaled up in size. For power applications, the f_T of InP/GaInAs pnp devices may even surpass that of npn transistors     

The two-dimensional model for the base surface current in integrated bipolar transistors and its applications

The recombination of minority carriers at the Si-SiO₂ interface has a great effect on bipolar devices. In this paper, the surface electrical properties of capacitors (MOS or MNOS) and gate-controlled npn transistors which are passivated by SiO₂ and Si0₂---Si₃N₄ films, respectively, are studied, and it is found that the Si0₂---Si₃N₄ dual dielectrical films can reduce the surface current in the base region. An improved theoretical model of the base surface current versus surface potential or gate voltage is set up on the basis of the work of Hillen and Holsbrink [Solid St. Electron. 26, 453–463 (1983)] for integrated bipolar transistors. The model successfully explains the experimental results of the variation of the base surface current of the gate-controlled integrated bipolar npn transistors with the gate voltage and provides a more accurate model for the computer simulation and the reliability analysis of the devices.     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

On the geometrical dependence of low-frequency noise in SiGe HBTs

We present an investigation of the dependence of low-frequency noise on device geometry in advanced npn silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The devices examined in this work have fixed emitter width (W_E = 0.4 μm), but varying emitter length (0.5 μm  L_E  20.0 μm), and thus the ratio of the emitter perimeter (P_E) to the emitter area (A_E) varies widely, making it ideal for examining geometrical effects. The SPICE noise parameter A_F extracted from these devices decreases with increasing L_E. Furthermore, the low-frequency noise measured on SiGe HBTs with significantly different P_E/A_E ratios suggests a possibility that the fundamental noise source for the diffusion base current may be located at the emitter periphery. Transistors with different distances between the emitter edge and the shallow trench edge (XEC), and shallow trench edge to deep trench edge (XTC), are also investigated. The SiGe HBTs with a smaller value of XEC have higher low-frequency noise, but no significant difference is found in devices with varying XTC. Explanations of the observed noise behavior are suggested.     

Double-step annealing and ambient effects on phosphorus implanted emitters in silicon

Emitters of npn silicon bipolar transistors have been made by a phosphorus implantation at 50 keV P⁺ to a dose of 1×10¹⁶ cm^?2. This was followed by high temperature processes to reduce lattice disorder, to drive-in the phosphorus atoms, and to form oxide layers. The first process step was carried out by using single- and double-step anneals in various ambients (dry N₂, dry O₂ and steam) while the drive-in and oxidation steps were common for all structures. Electrical measurements on emitter/base leakage current, low frequency (popcorn) noise and current gain showed that the annealing ambient had a major influence. The transistors with implanted emitters annealed in a dry N₂ ambient are comparable to commercial ones with thermally-diffused emitters. TEM observations on samples annealed in steam ambients revealed dislocatons extending into the sidewall of the emitter/base junction. This sidewall penetration of dislocations is the main origin of the degradation of the emitter/base junction characteristics.     

1f, g-r and burst noise induced by emitter-edge dislocations in bipolar transistors

Noise measurements conducted on npn bipolar transistors have revealed that the emitter-edge dislocations give rise to both $\text{1}\text{f}\text{and}\text{g-r}$ noise, the resulting noise increasing with the number of dislocations. In dislocated devices, an $\text{α ? 1.8 × 10}{}^{\mathrm{?4}}$ has been found which accounts for the base 1/f noise as mobility-fluctuation noise. A 1/ff² burst noise spectrum was observed when dislocations are clustered.     

双极晶体管的低剂量率电离辐射效应

通过对npn管和pnp管进行不同剂量率的电离辐射实验,研究了双极晶体管的低剂量率辐射效应.结果表明,双极晶体管在低剂量率辐照下电流增益下降更为显著,这是由于低剂量率辐照在氧化层中感生了更多的净氧化物正电荷浓度,致使低剂量率下过量基极电流明显增大.而辐照后npn管比pnp管具有更大的有效表面复合面积,致使前者比后者有更大的表面复合电流,从而导致了在各种剂量率辐照下,npn管比pnp管对电离辐射都更为敏感.     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

Investigation of deep traps in silicon–germanium epitaxial base bipolar transistors with a single polysilicon quasi self-aligned architecture

The electrical properties of Si/Si_1−xGe_x bipolar transistors have been analysed at temperatures ranging from 77 to 500 K. The investigated SiGe base transistors were fabricated using a BiCMOS single-polysilicon quasi self-aligned process, where base implant had been replaced by selective epitaxy on the base active area. At low temperature, static current–voltage measurements show a degradation of base current ideality, whereas collector current remains ideal over the whole temperature range. By studying forward and reverse currents at emitter–base and base–collector junctions, we have established that deep levels were involved in conduction phenomena at these junctions. Detailed measurements using capacitance transient spectroscopy (with different reverse and filling pulse voltages and different filling pulse durations) have revealed the presence of two deep levels along the periphery of the emitter. These deep levels have been found with identical characteristics at both junctions. It is demonstrated that these traps are most probably induced by the extrinsic base implantation.     

Generation–recombination noise in bipolar transistors

The generation–recombination (g–r) noise in bipolar junction transistors (BJTs) is due to the deep-level impurities in the p–n junctions. The larger the amplitude of g–r noise, the worse the quality of BJTs, so that measuring the amplitude of the g–r noise is way of estimating the reliability of BJTs. In some papers, it is assumed that the amplitude of g–r noise is proportional to the square of base current (I_b²), but in a few papers it has been reported that this relation is more complex. In this paper the amplitude of g–r noise versus base current is discussed, the theoretical and experiment results demonstrate that the g–r noise and burst noise signal may be observed only in a certain range of base current, and the law S(f)∝I_b² is not valid. It means that we must measure g–r noise and observe burst noise signal over a wide range of base current to estimate the concentration of deep-level impurities in p–n junction and hence the reliability of BJTs.     

Self-aligned complementary bipolar technology for low-powerdissipation and ultra-high-speed LSIs

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit     

辐照诱生的双极性线性稳压器的1/f 噪声退化研究

研究发现辐照能使双极线性稳压器LM117的输出1/f噪声性能退化。本文在研究双极线性稳压器LM117的辐照失效机理基础上,认为LM117的内部带隙基准是其噪声性能退化的关键部件,辐照引起的带隙基准内部的双极性晶体管的基极表面复合电流的退化,导致LM117输出1/f噪声发生退化。通过对比,可以看出1/f噪声比电参数敏感,也可以用来表征LM117辐照损伤。     

Origin of 1/f noise in lateral PNP bipolar transistors

1/f noise was measured on lateral bipolar PNP transistors over a temperature range of 220<T<450 K. Noise power spectral density measurements were performed simultaneously across two resistors connected in series with base and collector. The equivalent base current noise source S_IB has two dominant components. One is S_IBE that is between the base and the emitter, in parallel with r_π. The other is S_IBC coming from the surface recombination current at the neutral base, between the base and the collector. The extracted S_IB exhibited a near square law dependence on base current I_B. The noise remained nearly constant when the temperature was below 310 K. However, it presented strong temperature dependence when the temperature was beyond 310 K. Two different models are proposed for the noise in different temperature regions. For the high temperature region, the surface recombination velocity fluctuation model is proposed, which indicates that the noise is coming from the fluctuations in the surface recombination velocity at the neutral base surface. The tunneling assistant trapping model is responsible for the low temperature region, where the noise source is the carrier trapping–detrapping by the defects in the spacer oxide covering the surface of the depletion layer.     

Characterisation of emitter/base leakage currents in SiGe HBTs produced using selective epitaxy

SiGe heterojunction bipolar transistors have been fabricated using selective epitaxy for the Si collector, followed in the same growth step by non-selective epitaxy for the SiGe base and Si emitter cap. E/B leakage currents are compared with cross-section TEM images to identify sources of leakage currents associated with the epitaxy. In addition, the influence of the position of the extrinsic base implant with respect to the polysilicon emitter on the leakage currents is studied. The emitter/base leakage currents are modelled using Shockley–Read–Hall recombination, trap-assisted tunnelling and Poole–Frenkel (PF) generation. The position of the extrinsic base implant is shown to have a strong influence on the leakage currents. The PF effect dominates the emitter/base leakage current in transistors in which the collector area is smaller than the polysilicon emitter. This result is explained by penetration of the emitter/base depletion region into the p⁺ polysilicon extrinsic base at the perimeter of the emitter. These leakage currents are eliminated when the collector area is increased so that the extrinsic base implant penetrates into the single-crystal silicon at the perimeter of the emitter.     

High current gain 4H-SiC npn bipolar junction transistors

The authors report a common emitter current gain /spl beta/ of 55 in npn epitaxial-emitter 4H-SiC bipolar junction transistors. The spacing between the p+ base contact implant and the edge of the emitter finger is critical in obtaining high-current gain. V/sub CEO/ of these devices is 500 V, and V/sub CBO/ is 700 V.