Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Reliability studies and design improvement of mirror image CSP assembly

In this paper, both simulation and testing techniques were used to address the reliability issue of mirror chip scale package (CSP) assembly. First, finite element modeling was employed to study the stress and strain of a mirror image CSP with comparison to a single-sided CSP. The study clearly illustrates that the strain distribution is not equally distributed across both sides of the CSP. The highest strain on one side of the mirror image CSP is often larger than the other one, which reduced the reliability of the package as a whole. In order to study the effects on the reliability of the mirror image CSP assembly, several parameters, such as PCB board materials selection, board thickness and warpage, PCB via design and routing, were investigated. Moreover, a design of experiment matrix was constructed to identify significant factors to minimize the highest strain in solder joints of mirror image. The test vehicle was then designed and assembled. Thermal cycling (0 to 100 °C) and thermal shock tests were thereafter performed to the mirror image CSPs and single-sided CSPs to compare with the simulation results.     

Corner bonding of CSPs: processing and reliability

The use of chip-scale packages (CSPs) has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow provide the most common solution to improving mechanical reliability. However, capillary underfill dispense, flow, and cure steps and the associated equipment add cost and complexity to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print but before CSP placement. During reflow, the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement, and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and nonunderfilled CSPs. Finite-element modeling results for the drop test are also included.     

Overdriving reliability of chip scale packaged LEDs: Quantitatively analyzing the impact of component

The objective of this study is to quantitatively evaluate the impacts of LED components on the overdriving reliability of high power white LED chip scale packages (CSPs). The reliability tests under room temperature are conducted over 1000 h in this study on CSP LEDs with overdriving currents. A novel method is proposed to investigate the impact of various components, including blue die, phosphor layer, and substrate, on the lumen depreciation of CSP LEDs after aging test. The electro-optical measurement results show that the overdriving current can lead to both massive light output degradation and significant color shift of CSP LEDs. The quantitative analysis results show that the phosphor layer is the major contributor to the failure in early period aging test. For the long-term reliability, the degradations of phosphor and reflectivity of substrate contribute significantly on lumen depreciation. The proposed reliability assessment method with overdriving loadings can be usefully implemented for LED manufacturers to make a cost- and effective-decision before mass production.     

Reliability of new packaging concepts

Today, most of the microelectronics packaging needs are met by semiconductor devices in plastic surface mount (SM) packages. Microelectronics packaging of the future will be either bare chip or chip size/scale packaging (CSP). Of the 45 billion SM packaged ICs to be manufactured in 2000, CSPs will be a small 3.4% but growing at 62% (compound annual growth rate). The use of direct bonded chip-on-board and flip chip (FC) technology for custom solutions may not match the growth of CSPs. The popcorn problem of existing plastic packages has been solved in many ways including the use of hydrophobic composite encapsulants as the best solution and thorough bake-out and storage as the long-standing practical solution. The popcorn problem which was more severe with the smaller and thinner encapsulations of CSPs is also solved with modern hydrophobic materials and new non-paddle package designs. Further, there is good evidence that reliability is not impaired even by delaminations in the bulk of the encapsulations – small delaminations being an inevitable consequence of stress relaxation following transfer moulding. CSP and FC bump joint reliability is safeguarded both by good soldering practice and by effective underfill. High reliabilities are achievable with the range of new packages built from modern materials, with random failure rates down to 10 failure units, infant mortalities controlled to low levels by six sigma manufacturing processes and wearout lifetimes exceeding 100 years even in tropical operation.     

Processing and reliability of CSPs with underfill

The use of chip scale packages (CSPs) is rapidly expanding, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. This paper examines the assembly process with capillary and fluxing underfills. Issues of solder paste versus flux only, solder flux residue cleaning and reworkability are investigated with the capillary flow underfills. Fluxing underfills eliminate the issues of flux-underfill compatibility, but require placement into a predispensed underfill. Voiding during placement is discussed. To evaluate the relative performance of the underfills, a drop test was performed and the results are presented. All of the underfills significantly (5-6x) improved the reliability in the drop test compared to nonunderfilled parts. Test vehicles were also subjected to liquid-to-liquid thermal shock testing. The use of underfill improved the thermal shock performance by /spl ges/5x.     

Reliability evaluation of ultra-thin CSP using new flip-chip bonding technology––double-sided CSP and single-sided CSP

A high-density packaging technology has been developed that uses new flip-chip bonding technology with a thin IC and a thin substrate. Numerical analysis with the finite element method as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided chip-size packages (CSPs) could be expressed using a normal stress value in thickness, which is computed by the IC thickness and substrate type and thickness. The dependency of the life in double-sided CSPs could be expressed using a shear stress value in the vertical cross section, which is computed in IC thickness and substrate type and thickness, respectively.Moreover, a double-sided flip-chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional CSP.     

Investigation of the Role of Void Formation at the Cu-to-Intermetallic Interface on Aged Drop Test Performance

Chip-scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability requirement for these products. With the switch to lead-free solder, new reliability data must be generated. Most drop test reliability data reported for CSPs are for the as-built condition. However, the mechanical shock reliability over the life of the product is equally important. This paper provides a systematic study of surface finish (immersion Sn and immersion Ag) and reflow profile (cool down rate) on the drop test reliability of CSP assemblies. A limited experiment was also performed with organic solderability preservative (OSP)-coated boards. The Sn finish provides an initial Cu-Sn intermetallic layer, while the Ag finish and OSP coating allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop test results for assemblies as-built and as a function of aging at 125 degC are correlated with cross-sectional analysis of the solder joints. The mean number of drops to failure decreases by approximately 80% with aging at 125 degC through 480 h. Voids develop at the Cu-Sn intermetallic-to-Cu interface during high-temperature aging, but the crack path is through the intermetallic layer and does not propagate from void-to-void. Thus, it can be concluded that the voids do not contribute to the decrease in drop test survivability observed in this study     

Board-level reliability of Pb-free solder joints of TSOP and various CSPs

To evaluate various Pb-free solder systems for leaded package, thin small outline packages (TSOPs) and chip scale packages (CSPs) including leadframe CSP (LFCSP), fine pitch BGA (FBGA), and wafer level CSP (WLCSP) were characterized in terms of board level and mechanical solder joint reliability. For board level solder joint reliability test of TSOPs, daisy chain samples having pure-Sn were prepared and placed on daisy chain printed circuit board (PCB) with Pb-free solder pastes. For CSPs, the same composition of Pb-free solder balls and solder pastes were used for assembly of daisy chain PCB. The samples were subjected to temperature cycle (T/C) tests (-65/spl deg/C/spl sim/150/spl deg/C, -55/spl deg/C/spl sim/125/spl deg/C, 2 cycles/h). Solder joint lifetime was electrically monitored by resistance measurement and the metallurgical characteristics of solder joint were analyzed by microstructural observation on a cross-section sample. In addition, mechanical tests including shock test, variable frequency vibration test, and four point twisting test were carried out with daisy chain packages too. In order to compare the effect of Pb-free solders with those of Sn-Pb solder, Sn-Pb solder balls and solder paste were included. According to this paper, most Pb-free solder systems were compatible with the conventional Sn-Pb solder with respect to board level and mechanical solder joint reliability. For application of Pb-free solder to WLCSP, Cu diffusion barrier layer is required to block the excessive Cu diffusion, which induced Cu trace failure.     

Solder joint reliability and characteristics of deformation and crack growth of Sn-Ag-Cu versus eutectic Sn-Pb on a WLP in a thermal cycling test

Sn-Ag-Cu (SAC) is now recognized as the standard lead free solder alloy for packaging interconnect in the electronics industry. This paper analyzes the performance of both SAC and eutectic Sn-Pb solder alloys on Kulicke & Soffa's (K&S') Ultra CSP/spl reg/ wafer level package (WLP) at a thermal cycling (TC) test. The Ultra CSP standard Al/Ni-V/Cu under bump metallurgy (UBM) system was used to analyze if this UBM system with SAC solder would produce acceptable reliability in the TC test. In this study, two TC tests were performed. In the first test, two parts were removed from the TC chamber about every 200 cycles to investigate the characteristics of deformation and crack growth in the SAC and eutectic Sn-Pb Ultra CSP solder joints during TC testing. These TC test results showed that both the SAC and eutectic Sn-Pb Ultra CSPs exhibited normal solder joint fatigue failures during the testing. The SAC Ultra CSP had an equal or 18% higher Weibull life than the eutectic Sn-Pb one. Based on these results it was concluded that the SAC Ultra CSP with the Al/Ni-V/Cu UBM system produces acceptable solder joint reliability in a TC test. The results also revealed that the deformation and crack growth characteristics of the SAC and eutectic Sn-Pb Ultra CSP solder joints were significantly different. The eutectic Sn-Pb solder joints showed significant inelastic shear deformation during the TC testing while the SAC solder joints did not display significant inelastic deformation even at the high temperature regime of the TC test.     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

Novel reworkable fluxing underfill for board-level assembly

Underfills are traditionally applied for flip-chip applications. Recently, there has been increasing use of underfill for board-level assembly including ball grid arrays (BGAs) and chip scale packages (CSPs) to enhance reliability in harsh environments and impact resistance to mechanical shocks. The no-flow underfill process eliminates the need for capillary flow and combines fluxing and underfilling into one process step, which simplifies the assembly of underfilled BGAs and CSPs for SMT applications. However, the lack of reworkability decreases the final yield of assembled systems. In this paper, no-flow underfill formulations are developed to provide fluxing capability, reworkability, high impact resistance, and good reliability for the board-level components. The designed underfill materials are characterized with the differential scanning calorimeter (DSC), the thermal mechanical analyzer (TMA), and the dynamic mechanical analyzer (DMA). The potential reworkability of the underfills is evaluated using the die shear test at elevated temperatures. The 3-point bending test and the DMA frequency sweep indicate that the developed materials have high fracture toughness and good damping properties. CSP components are assembled on the board using developed underfill. High interconnect yield is achieved. Reworkability of the underfills is demonstrated. The reliability of the components is evaluated in air-to-air thermal shock (AATS). The developed formulations have potentially high reliability for board-level components.     

High reliability, high density, low cost packaging systems formatrix systems for matrix BGA and CSP by vacuum printing encapsulationsystems (VPES)

Ball grid array (BGA) and chip scale package (CSP) packaging markets are increasing. In general, transfer molding systems are used for these packaging processes. However, transfer molding systems are difficult to change the model for high expensive metal die. This paper describes a unique vacuum printing encapsulation system (VPES) we developed to solve such problems with lower cost than transfer molding. We used matrix type BGA and CSP for this test. Matrix type BGA and CSP make it easy to use printing technology for die-bonding, packaging, marking, and flux coating process. The total cost of this packaging is cheaper than the transfer molding process. We developed very low warpage and high reliability epoxy resin for matrix BGA and CSP. We succeeded in achieving high reliability and low cost packaging systems with this technology     

Epoxy-based aqueous-processable photodielectric dry film andconductive ViaPlug for PCB build-up and IC packaging

DuPont formulated a new generation of photoimageable permanent resists and conductive ViaPlug polymer to be used as building blocks for sequential build-up of printed circuit boards (PCB's), multichip module-laminates (MCM-Ls), and plastic integrated circuit (IC) packages. The buzzwords for these structures are high density interconnection structures (HDIS) and microvias. The conventional method of making PCB's and MCM-Ls is a sequential lamination of innerlayer cores or interplanes, followed by at least one mechanical drilling. In this paper we will discuss a new approach of using semi-additive plating which means starting with a multilayer core, mechanically drilling for through hole connection, filling the through-hole with conductive ViaPlug, then adding layers of dielectric to make blind or buried vias for interconnection and routing of circuits, and heat dissipation. The paper will discuss the challenges in each application, relevant industry specifications for each application, and the dielectric and conductor materials properties to meet the challenges. From the viewpoint of technology choices, we will compare photoimaging versus laser ablation and plasma etching. Lastly, we will discuss our reliability data developed internally and in conjunction with several consortia     

Wafer level packaging of a tape flip-chip chip scale packages

The advent of chip scale packages (CSPs) within the semiconductor community has led to the development of wafer scale assembly (WSA) or wafer level packaging (WLP) manufacturing in order to raise assembly efficiencies and lower operating costs. Texas Instruments (TI) has developed a unique WLP process for forming flip-chip, ball grid array packages. The die inputs and outputs of the TI CSP are connected through solder bumps to a polyimide film interposer. Solder balls on the other side of the interposer complete the electrical connection to a customer’s printed circuit board. A wafer-sized array of interposers designed to match the pattern of dies on a wafer is aligned and reflowed to a bumped wafer. The TI WLP process is completed by singulating the CSPs from the wafer using standard wafer saw equipment.Attachment of the interposer to the die as well as applying the die and board level solder bumps are carried out in wafer form using a new bumping technology called Tacky Dots™. Tacky Dots uses an array of sticky dots formed in a photosensitive coating laminated to a polyimide film for transferring and attaching solder spheres to semiconductor substrates. A populated film containing one solder sphere per Tacky Dot is positioned over the wafer or interposer and lowered until the spheres contact the pads. A reflow process transfers the spheres from the film to the wafer or interposer and the film is removed once the spheres have frozen.This paper illustrates the process steps and custom equipment developed for forming the TI CSP. The strategic use of finite element modeling for optimizing the design of the package is outlined. The paper concludes by summarizing the current package level reliability results.     

Drop impact reliability of edge-bonded lead-free chip scale packages

This paper presents the drop test reliability results for edge-bonded 0.5 mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board. The test boards were subjected to drop tests at several impact pulses, including a peak acceleration of 900 Gs with a pulse duration of 0.7 ms, a peak acceleration of 1500 Gs with a pulse duration of 0.5 ms, and a peak acceleration of 2900 Gs with a pulse duration of 0.3 ms. A high-speed dynamic resistance measurement system was used to monitor the failure of the solder joints. Two edge-bond materials used in this study were a UV-cured acrylic and a thermal-cured epoxy material. Tests were conducted on CSPs with edge-bond materials and CSPs without edge bonding. Statistics of the number of drops-to-failure for the 15 component locations on each test board are reported. The test results show that the drop test performance of edge-bonded CSPs is five to eight times better than the CSPs without edge bonding. Failure analysis was performed using dye-penetrant and scanning electron microscopy (SEM) methods. The most common failure mode observed is pad lift causing trace breakage. Solder crack and pad lift failure locations are characterized with the dye-penetrant method and optical microscopy.     

Effect of the drop impact on BGA/CSP package reliability

In this study, ball grid arrays (BGAs) and chip size packages (CSPs) were evaluated with respect to their solder joint reliabilities under drop impacts. The correlation between solder joint stresses and motherboard strains was confirmed by numerical analysis, and the motherboard strains caused by the drop impacts were measured to evaluate the BGA/CSP reliability. The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strain and disperses the stress concentrated on a solder joint.     

Lead-free chip scale packages: assembly and drop test reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.     

Chip-scale packaging of power devices and its application inintegrated power electronics modules

A power electronics packaging technology utilizing chip-scale packaged (CSP) power devices to build three-dimensional (3-D) integrated power electronics modules (IPEMs) is presented in this paper. The chip-scale packaging structure, termed die dimensional ball grid array (D²BGA), eliminates wire bonds by using stacked solder joints to interconnect power chips. D²BGA package consists of a power chip, inner solder caps, high-lead solder balls, and molding resin. It has the same lateral dimensions as the starting power chip, which makes high-density packaging and module miniaturization possible. This package enables the power chip to combine excellent thermal transfer, high current handling capability, improved electrical characteristics, and ultralow profile packaging. Electrical tests show that the V_CE(sat) and on-resistance of the D²BGA high speed insulated-gate-bipolar transistors (IGBTs) are improved by 20% and 30% respectively by eliminating the device wirebonds and other external interconnections, such as the leadframe. In this paper, we present the design, reliability, and processing issues of D²BGA package, and the implementation of these chip-scale packaged power devices in building 30 kW half-bridge power converter modules. The electrical and reliability test results of the packaged devices and the power modules are reported     

0.5 mm间距CSP焊接工艺研究

随着对各种电子产品，尤其是消费类电子产品的便携性和多功能的追求，CSP等新型封装器件(封装尺寸约为芯片本身尺寸的1．2倍)便应用到这些产品的设计中去。CSP器件的引脚间距有0．8mm、0．75mm、0．65mm、0．5mm等。为了便于以后产品设计和生产的需要，就CSP器件在PWB设计和焊接两方面进行研究，侧重于焊接方面。