Ultra-high-density interconnection technology of three-dimensional packaging

The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.     

A new methodology for the identification of ball bond degradation during high-temperature aging tests on devices in standard plastic packages

We describe a new methodology for the “in situ” identification of wire-bond degradation at early stages during high-temperature aging tests on devices with standard plastic packages. This methodology is based on the measurement of the changes in wire bond resistance, which is deduced from the I(V) characteristics of the ESD protection diodes on each contact pad of the circuit. In a first stage, the measurement procedure is described, with emphasis on the initial temperature calibration. This procedure allows for an “in situ” measurement sequence, where the packages stay in the aging chamber, at elevated temperature, during the electrical tests on the pad connections performed at different aging durations. By following accurately the package temperature, using a thermocouple, it is possible to correct for slight changes and thus get a reliable I–V measurement for each interconnection. In the second stage, the aging test results are described, showing the evolution of each individual interconnection. We were able to identify the onset of wire-bond degradation through the progressive increase of their resistance. To allow for better determination of the degradation process, once an increase in wire bond resistance was detected, complete I(V) curves were recorded at the pin(s) of interest. For each pin of a TQFP64 package, the tests were performed at least twice a day, with increased density when initial failure is detected (one complete measurement every 3 h). This strategy allowed for the detection of different behaviors on the wire bonds: good ball bonds (i.e. ball bonds with no change in their resistance), ball bond with intermittent opens (these ball bonds are in the process of degradation, and thermo-mechanical stresses induced in the resin by very small temperature changes are sufficient to open or close the circuits) and completely destroyed ball bonds, for which the resistance stays in an “high” level. This approach to wire-bond degradation in plastic packages is very powerful in terms of the number of interconnections which can be followed “in real time” and especially has the advantage, over other classical approaches, that the devices under test stay operational, contrary to what occurs with other types of destructive testing. These electrical test results are compared with metallographic investigations performed after a series of mechanical tests on the ball bonds (wire pull/ball shear tests) on a set of identical devices which undergone exactly the same High Temperature Storage (HTS) aging for 2000 h at 165 °C.     

Next generation of 100-/spl mu/m-pitch wafer-level packaging and assembly for systems-on-package

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 /spl mu/m by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-/spl mu/m pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final "optimum" design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with a coefficient of thermal expansion of 10 ppm/K or lower.     

Extension of a multilayer interconnection technology in MCM-Si with opto-electronic facilities

The increasing I/O-density of today’s packages is dealt with by using multilayer modules. Since there is also a trend towards faster interconnections by using optics, the extension of the interconnection module with V-grooves is in high demand. This paper reports on the electro-optical extensions of an earlier developed standard MCM-Si technology (Lernout et al., Journal of IMAPS (Europe) 1998; 15(1): 39–42; Ref. 1). The technology aspects of this standard MCM-Si technology are presented.The extended thin-film multilayer module is built up using two metal and three insulator layers. Additionally an implementation with low TCR resistors (NiCr) can be made. Fiber holding structures, namely V-grooves, are created into the bulk (100) silicon substrate by means of an anisotropic etching, performed in aqueous KOH. A passivation layer of silicon nitride, optimised towards low silicon content, served as protection mask during the KOH etching. The compatibility of this aggressive wet etching step with other processing steps is discussed. As for the insulators in the multilayer module, these high quality PECVD (Plasma Enhanced Chemical Vapour Deposition) layers are optimised towards low stress content and uniformity.Subsequently, the use of this interconnection substrate as a motherboard in multichip modules (MCM) is considered. The extension of the motherboard with V-grooves makes it possible to integrate opto-electronic (O/E) components, fibers and electronics on the same MCM-Si. Some of the major advantages are: low cost solution (saving non-used silicon area), compact assembly (carriers of fibers integrated with electronics), ability to reach higher frequencies (shorter interconnection distances),… Also low coupling losses between laser and fiber are achieved: the accuracy of V-grooves in silicon permits to place the fiber with high precision, and the self-aligning property of solder assures the control over the flip-chip (FC) mounted O/E-components (e.g. laser diodes).     

MT™-compatible connectorisation of VCSEL and RCLED arrays to plastic optical fibre ribbon for low cost parallel datalinks

For the realisation of MT™-compatible direct connectorised modules, a PMMA-based interconnection scheme, using index alignment is developed. Plastic pieces are accurately positioned with respect to the chips and then fixed with epoxy, following an index-alignment strategy. Alignment accuracies in the range of 5–10 μm have been achieved, which is sufficient to have good coupling efficiencies in view of the relaxed alignment tolerances when coupling to small diameter (125 μm) plastic optical fibre. The chips are assembled in commercially available packages, which are then mounted on PCB boards. First coupling measurements on fully assembled modules, using a red (670 nm) 1×8 VCSEL-array and an infrared (980 nm) 1×8 RCLED (resonant cavity LED) array, are successfully carried out.     

A prognostic method for the embedded failure monitoring of solder interconnections with 1149.4 test bus architecture

This paper describes the feasibility of accurate low frequency measurements in predicting the breakdown of modern lead free ball grid array (BGA) interconnections. In these measurements, performed partly with 1149.4 analogue boundary scan, ceramic BGA modules measuring 15×15 mm in width, with 9×9 ball matrixes, were attached on an FR-4 printed wiring board (PWB) and thermally cycled over a temperature range of −40 to +125 °C. The condition of corner interconnections was monitored using the developed measurement methods and construction. In-situ measurements were performed with a datalogger during temperature cycling, accompanied with 1149.4 mixed-signal test bus measurements of corner interconnections performed between cycling intervals. In addition, the measurements were complemented by scanning acoustic microscopy and, X-ray. Monitoring corner interconnections by a simple, low-frequency voltage measurement method with embedded test constructions gives an early warning indication well before the electrical interconnection failures. Of two studied interconnection compositions, the ones with plastic core solder balls (PCSB) proved to be more reliable than the ones with 90/10 PbSn balls.     

High-frequency SPICE model of anisotropic conductive film flip-chipinterconnections based on a genetic algorithm

This paper firstly reports on the high-frequency SPICE model of the ACF flip-chip interconnections up to 13 GHz. The extraction process is based on an optimization procedure, called a genetic algorithm, which is known as a robust optimization tool. The proposed equivalent circuit model of the ACF interconnection can readily be used in SPICE circuit simulations for signal integrity analysis of high-frequency packages. Two different ACF interconnections were studied using the Au-coated polymer ball and Ni-filled ball. The extracted models of the two ACFs were found strongly dependent on not only size and rigidity of the conducting balls, but also on their magnetic permeability     

A simple model for the mode I popcorn effect for IC packages

A simple model for the Mode I popcorn effect is presented here for packages with rectangular die pad (P-DSO). A package “stability parameter”, relating to its moisture sensitivity, is derived from the popcorn model. It describes the critical factors for a robust package - molding compound properties and package, leadframe design for a given preconditioning and soldering process. Furthermore, nomograms generated from the model enable an easy estimation of moisture sensitivity levels (between 1 and 5) of packages with different die pad sizes and molding compound underpad thicknesses and for different soldering temperatures ranging from 220°C to 260°C (Pb-free soldering).     

Solder joint reliability of indium-alloy interconnection

Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.     

Architectural framework for optical frequency division multiplexingsystems based on regular space-frequency interconnections

The paper describes a multistage interconnection network (MIN) with regular interconnections in three dimensions (two space dimensions and the third dimension is the frequency) and dimension-dependent switches. (Regular interconnections mean that the same interconnection principles are applied throughout the stages of the MIN.) The frequency domain is organized by introducing artificial dimensions. The architecture is interpreted as an optical frequency division multiplexing (OFDM) system with multidimensional interconnections and switches where the dimension is an additional design parameter. The multidimensional interconnections may be implemented using a combination of space and frequency channels. The frequency interconnections (data movements between channels) are expressed by the Kronecker product (KP) of permutation matrices. In this case the number of frequency conversion (FC) operations and the number of frequency channels crossed during the generation of interconnections and switching decreases. The architectural principles presented are of general interest for the study of transmission and processing in arbitrary large scale interconnection systems implemented in the 3-D physical space     

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Laser THz emission microscope as a novel tool for LSI failure analysis

We have proposed and developed a novel technique for a non-contact inspection of defective interconnections in an LSI chip using a laser terahertz emission microscope (LTEM). The LTEM measures the THz emission images of an LSI chip by scanning it with fs laser pulses. When a fs laser pulse irradiates a p–n junction in an LSI chip, transient photocurrent flows into interconnections resulting in the emission of the THz pulse into free space. We investigated the characteristics of the THz emissions from simple test element group samples which consist of p–n junctions connected to metal lines. It was found that the metallic lines connected to photo-excited p–n junctions worked as THz emission antennae which enhance the emission efficiency of THz pulses near their resonant frequencies corresponding to the line lengths. This result indicates that THz emission signals from p–n junctions in circuits strongly depend on the structure of the interconnections. We show the successful results on the inspection of defective interconnections in MOSFET devices and C7552 ISCAS’85 benchmark circuits using LTEM. By comparing the THz emission images between a normal circuit and a defective one, it is possible to identify the p–n junctions connected to the defective interconnections without electrical contacts.     

A simple moisture diffusion model for the prediction of optimal baking schedules for plastic SMD packages

The moisture concentration at the chip surface is the important parameter for the moisture sensitivity of the P-MQFP80 product considered here. When the critical moisture concentration at the die surface is reached, delamination occurs after soldering shock, e.g at 240°C. This critical moisture concentration, which can be determined by experiments conducted at 30°C/60% relative humidity (RH) followed by soldering shock, allows to predict the product’s moisture performance at other ambient conditions. In the case studied here, prediction was done at a customer use condition of 30°C/85% RH. Furthermore, this work showed that preconditioning of plastic packages not only induces the onset of delamination at the die surface but it appears to weaken the adhesion at this interface as well. As a result, delamination failure starts to occur earlier (i.e. within shorter moisture exposure time) in the devices tested after subsequent thermal cycling stress test. A simple moisture diffusion analytical model is proposed here for predicting the optimal baking schedules for plastic SMD packages.     

Correlation between localized strain and damage in shear-loaded Pb-free solders

A digital image correlation (DIC) algorithm was employed to measure microscopic strain-field evolution in shear-loaded model solder interconnections made out of a number of Sn-based alloys. Four different solder alloys studied were Sn–36Pb–2Ag, Sn–3.8Ag–0.7Cu (SAC), Sn–3.3Ag–3.82Bi, and Sn–8Zn–3Bi. The measured strain fields were correlated with damage observed at the scale of the sample, and at microscopic length scales.Local strain differs significantly from applied global strain and has been shown to depend on the geometry of the samples as well as the microstructure (on a grain level) of the solder.Strain fields in all solder interconnections were found to localize near but not at the solder–substrate interface and along grain boundaries in the solders. The eventual failure path as observed on the scale of the sample (parallel to the two solder–substrate interfaces with a cross-over from one interface to the other somewhere in the connection) showed a good correlation with measured strain fields in all interconnections.In contrast to the similarity on a macroscopic scale, on a microscopic scale the failure mechanisms were observed to be material specific.     

Transient IR imaging of light and flexible microelectronic devices

An advanced method for the quality assessment of microelectronic assemblies has been developed by combining IR thermography and several techniques for stimulation by transient temperature fields. The method exploits singularities in materials and interconnections by the observation of perturbations in transient heat flow phenomena. For very light microelectronic systems like chip-on-flex assemblies a method was developed taking advantage of short stimulations by photoflash. Such a method provided possibilities for detecting defects on the level of a single interconnection with a pitch of 80 μm. In addition, a programmable array of thermo-electric converters, prepared for the testing of a large variety of microelectronic assemblies, was also used to perform transient IR imaging for chip-on-flex assemblies.     

Vibration fatigue reliability of BGA-IC package with Pb-free solder and Pb–Sn solder

In this paper, a new method is proposed for evaluating the high-cycle fatigue strength of BGA (Ball Grid Array) packages with Pb-free solder and Pb–Sn solder due to vibration. An attached weight induced mixed mode stress in the solder ball of a package was used. To consider the effect of the mixed mode stress that occurred in a solder ball and the frequency to fatigue strength of the solder ball, a test was carried out with the three kinds of weights (σ_n/τ_n = 4, 5, and 6) at various frequencies (10–27 Hz). To clarify the effect of frequency, a nonlinear analysis with a viscoplastic model was carried out within the range of 0.001–3450 Hz. From the continuous observation of the cross-section of the package and finite element method (FEM) analysis results, it was revealed that the maximum principal stress is the driving force to package failure. Although an intermetallic compound in both packages and a Pb-rich region in a Pb–Sn solder based package were confirmed by EDX microprobe analysis, they do not contribute to the initiation of a crack in a solder ball. The fatigue strength of the Pb-free solder and Pb solder was evaluated on the basis of the maximum principal stress calculated by FEM and the experimental results.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin–bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin-plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

An investigation of solar cell interconnection schemes within CPV modules using a validated temperature‐dependent SPICE network model

In this paper, we present a temperature‐dependent network model of a concentrator photovoltaic (CPV) module. The ability of this network model to calculate different interconnection schemes within CPV modules is validated, and there is good agreement between the measured and calculated data. The model is used to quantify the influence of an inhomogeneous current and of a temperature distribution between the solar cells on the power output of a module. The different interconnection schemes that combine parallel and series connections are compared. The optimal interconnection scheme strongly depends on the variations in the short current densities and temperature differences between the solar cells as well as on the risk of ‘sudden death’ of individual solar cells. Optimal interconnection schemes for several scenarios are developed. A combination of parallel and series interconnections is found to be the most robust interconnection. Copyright © 2012 John Wiley & Sons, Ltd.     

Physical models and algorithms for optoelectronic MCM layout

Future computers will need to incorporate the parallelism of optical interconnections in order to achieve projected performance within reasonable size, power and speed constraints. This is necessary since optical interconnections have advantages in size, power, and speed over “long” distance communication. These features make optical interconnects ideal for inter-module connections in multichip module systems. Free-space optical interconnection can be one form of optical interconnections. Computer generated holograms (CGHs) are extremely attractive optical components for use in free space optical interconnections due to their ability to be computer designed. We will show that the fabrication limitations of CGHs for general interconnection networks require the need for placement algorithms for large processing element (PEs) arrays. In this paper, we will demonstrate that these fundamental CGH fabrication limitations greatly influence the computer aided design of optoelectronic interconnect networks that utilize CGHs for optical interconnections. Specifically, we show that the minimum feature size directly affects the logical placement of processing elements. Various physical models for free-space optical interconnects in parallel optoelectronic MCM systems are then identified from which we derive several logical models for analysis. We then analyze these cases and present algorithms to solve the associated layout problems. Design examples are given to illustrate the benefits of utilizing these placement algorithms in real optoelectronic interconnection networks     

Integrated optical interconnections

The use of optical interconnections between processors, boards, chips, and gates in electronic digital systems to overcome the current performance limitations is described. The advantages of optical interconnections in relation to the interconnection distance, the data capacity, and the interconnection functions are presented. The devices which will support practical implementation of optical interconnections and the integration of optical interconnection devices are discussed. The development of future integrated optoelectronic materials, processing, and fabrication technologies to support integrated optical electronics is also discussed