Novel Design for High Speed and Resolution Delta-sigma A/D Converter

The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta- sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching（DEM） and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.     

Time-interleaved oversampling convertors

A new architecture is proposed which exploits the time-interleaving concept to increase the oversampling ratio in delta-sigma modulators. It is shown that the effective oversampling ratio is increased by a factor M through the use of M interconnected modulators. Although a high speed sample-and-hold circuit is still required for an analogue-to-digital convertor, speed constraints are significantly reduced for the majority of analogue parts such as loop filters, A/D and D/A blocks.<>     

A low-power reconfigurable analog-to-digital converter

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of ±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power     

A 2.5-V sigma-delta modulator for broadband communicationsapplications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-μm double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply     

A 5-V single-chip delta-sigma audio A/D converter with 111 dBdynamic range

A 5-V 24-b audio delta-sigma A/D converter has been developed. The single chip integrates stereo delta-sigma modulators, a voltage reference, and a decimation filter. A fourth-order cascaded delta-sigma modulator using a local feedback technique was employed to avoid overload without sacrifice in noise performance. A two-stage decimation filter architecture which reduces digital noise was developed. A new multistage comb filter was used for the first-stage, and a bit-serial finite impulse response (FIR) filter was used for the second stage. The 25.8 mm² chip was fabricated in 0.7-μm CMOS with low threshold MOS devices. Measured results show 111 dB dynamic range and 103 dB peak signal-to-(noise plus distortion)S/(N+D)     

20位∑-△A/D转换器的设计

文章介绍了20位、5V单电源过采样∑-△A/D转换器,根据精度与阶数和过采样比的关系,设计了4阶蒡-驻调制器。在∑-△调制器中添加了局部负反馈,使转换器能对满量程(FS)输入信号进行精确转换;在梳状滤波器后面添加了补偿电路,补偿梳状滤波器在基带内的衰减,使基带内的纹波小于0.001dB。本电路采用0.6滋mCMOS工艺,电路的结构和精度通过了HSPICE、STAR-SIM等EDA软件的验证。     

A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth

A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.     

High dynamic range InP HBT delta-sigma analog-to-digital converters

To date, the development of multifunction multicarrier digital receivers for cellular base station and military communications applications has been limited by the demanding dynamic range requirements for the analog-to-digital converter (ADC). The use of oversampling delta-sigma modulators provides a promising approach to overcoming the dynamic range barriers Nyquist-rate converters face in the same applications. This paper discusses issues involved in the design of high-speed high dynamic range wide-band delta-sigma ADCs for such communications applications. Test results of prototype designs are also presented. The delta-sigma modulators described in this paper operate at sampling frequencies ranging from 1 to 2.5 GHz with center frequencies ranging from dc to 100 MHz, providing between 74 and 84.2 dB signal-to-noise ratio (12 and 13.7 bits) for bandwidths of 25 and 12.5 MHz, respectively. The loop filters are continuous-time low-pass and bandpass implementations of order 6 and 10, and were fabricated in an InP heterojunction bipolar (HBT) technology. A typical tenth-order design consumes 6 W of power and occupies a die area of 23.5 mm/sup 2/.     

Wideband cascade delta-sigma modulator with digital correction forfinite amplifier gain effects

The authors present an alternative approach to reducing the effects of finite amplifier open-loop gain in cascade delta-sigma modulators. The proposed gain compensation is carried out in the digital domain and thus requires no additional analogue circuitry. The method is illustrated by the example of a double third-order cascade circuit which, when properly compensated for finite gain effects, can yield 1-20 bit resolution with oversampling ratios as low as 16-24     

An efficient /spl Delta//spl Sigma/ ADC architecture for low oversampling ratios

As the demand for /spl Delta//spl Sigma/ (delta-sigma) analog-to-digital converters (ADCs) with higher bandwidth and higher signal-to-noise ratio (SNR) increases, designers have to look for efficient structures with low oversampling ratio (OSR). The Leslie-Singh or M-0 MASH architecture is often used in such applications. Based on this architecture, a reduced-sample-rate structure was introduced, which needs less chip area and power, but increases the noise floor. This paper describes a modification of the reduced-sample-rate structure which realizes an optimized transfer function, and avoids an SNR loss. In fact, it increases the SNR for high-order modulators. The method can also be applied to one-stage modulators. Simulation results for different MASH ADCs and sensitivity analysis verify the usefulness of the proposed technique.     

A monolithic 2-b delta-sigma A/D converter

A monolithic 20-b analog-to-digital (A/D) converter using oversampling techniques which is implemented in standard 3-μm CMOS technology is described. The integrated circuit contains a fourth-order delta-sigma modulator and a digital finite-impulse-response filter and decimator. The modulator consists of a continuous-time chopper-stabilized front end, and a switched-capacitor loop filter and comparator. The dynamic range is 123 dB over a DC-to-500-Hz bandwidth, and the signal-to-noise-harmonic-distortion ratio is 126 dB. The chip consumes 125 mW power and has an area of 29.25 mm²     

An oversampling converter for strain gauge transducers

An oversampling converter that directly digitizes low-level strain gauge transducer outputs is presented. An instrumentation amplifier and two independent chopper-stabilized delta-sigma modulators amplify and convert the transducer's output and excitation. Digital division of the two independent conversions produces a 20-b ratiometric measurement. Drift due to external thermocouple junctions and RF rectification is eliminated by AC excitation of the transducer. Interference (50/60 Hz) is eliminated by a digital FIR filter that has a -3 dB bandwidth of 15 Hz. Offset and gain errors are corrected by digital calibration. The input-referred noise of this converter is 150 nV_rms and the linearity is 110 dB. The converter gain and offset drifts are less than 2.5 p.p.m./°C and 15 nV/°C, respectively. This 2-μm CMOS chip consumes 30 mW of power and has an area of 25.5 mm²     

A 114-dB 68-mW Chopper-stabilized stereo multibit audio ADC in 5.62 mm/sup 2/

A multibit delta-sigma audio stereo analog-to-digital converter has been developed. It employs a fifth-order single-loop 17-level delta-sigma modulator with an input feedforward gain stage. A second-order mismatch shaping (DEM) circuit is utilized to remove tones and nonlinearities caused by capacitor mismatch of the feedback digital-to-analog converter. The implementation of the DEM block introduces minimum latency into the delta-sigma feedback loop. Chopper stabilization is applied to the first integrator to eliminate the 1/f noise. The converter achieves 114-dB dynamic range and -105-dB total harmonic distortion over the 20-kHz audio band. This single chip includes stereo analog modulators, bandgap reference, serial interface, and a two-stage decimation filter, occupies 5.62-mm/sup 2/ active area in a 0.35-/spl mu/m double-poly, three-metal CMOS process and dissipates only 55-mW power in the analog circuits.     

A CMOS stereo 16-bit D/A converter for digital audio

A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-/spl mu/m CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.     

A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process

A 14-bit 8/spl times/ oversampling delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for wide-band communication applications has been developed. By using a novel architecture, a high maximum out-of-band quantization noise gain (Q/sub max/) is realized, which greatly improves the SNR and tonal behavior. The ADC employs a fifth-order single-stage structure with a 4-bit quantizer. It achieves 82-dB SNDR and 103-dB SFDR at 4-MHz conversion bandwidth with a single 1.8-V power supply.     

A continuous time delta-sigma modulator with reduced clock jitter sensitivity through DSCR feedback

The performance of continuous time delta-sigma modulators is limited by their large sensitivity to feedback pulse-width variations caused by clock jitter in their feedback DACs. To mitigate that effect, a dual switched-capacitor-resistor feedback DAC technique is proposed. The architecture has the additional benefit of reducing the typically high switched-capacitor-resistor DAC output peak currents, resulting in reduced slew-rate requirements for the loop-filter integrators. The feedback technique has been implemented with a third order, 3-bit delta-sigma modulator for a low power radio receiver, in a 65 nm CMOS process, where it occupies an area of 0.17 mm². It achieves an SNDR of 70 dB over a 125 kHz bandwidth with an oversampling ratio of 16. The power consumption is 380 μW from a 900 mV supply.     

A low oversampling ratio 14-b 500-kHz ΔΣ ADC with aself-calibrated multibit DAC

Delta-sigma (ΔΣ) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz     

Cascade delta-sigma modulator with pseudo-differential comparator-based switched-capacitor gain stage

A low-power, multi-stage delta-sigma modulator with comparator-based switched-capacitor (CBSC) gain stages is presented. The presented design eliminates the need for operational amplifiers and replaces them by comparators with current sources at their outputs to alleviate the effects of continued technology scaling on analog and mixed-signal circuits. The proposed technique significantly reduces power consumption and can be applied to switched-capacitor delta-sigma modulators of arbitrary order. Based on the proposed methodology, a 2-1 cascade, single-bit, pseudo-differential switched-capacitor delta-sigma modulator is developed and achieves a SNDR of 76.8 dB with an oversampling ratio of 64 at a clock frequency of 8 MHz.     

A 13-b 40-MSamples/s CMOS pipelined folding ADC with backgroundoffset trimming

Two key concepts of pipelining and background offset trimming are applied to demonstrate a 13-b 40-MSamples/s CMOS analog-to-digital converter (ADC) based on the basic folding and interpolation architecture. Folding amplifier stages made of simple differential pairs are pipelined using distributed interstage track-and-holders. Background offset trimming implemented with a highly oversampling delta-sigma modulator enhances the resolution of the CMOS folders beyond 12 bits. The background offset trimming circuit continuously measures and adjusts the offsets of the folding amplifiers without interfering with the normal operation. The prototype system is further refined using subranging and digital correction, and exhibits a spurious-free dynamic range (SFDR) of 82 dB at 40 MSamples/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are about ±0.5 and ±2.0 LSB, respectively. The chip fabricated in 0.5-μm CMOS occupies 8.7 mm² and consumes 800 mW at 5 V