Adaptor realisations for wave switched-capacitor filters with reduced capacitance spread

The design of wave SC adaptors with very low capacitance spread is described and illustrated for the case of the unit-element cascade filter. The adaptors are canonic in the number of operational amplifiers and are parasitic-insensitive.     

Alternative realisations of switched-capacitor floating inductors

Several switched-capacitor circuits simulating grounded and floating inductors have been published recently. Several alternative realizations are presented of s.c. inductors using one operational amplifier, which can be derived from a configuration reported previously.     

MOS switched-capacitor filters

In the past several years, much progress has been made in bringing the economies of integrated-circuit technology to bear on the realization of voiceband frequency selective filters. This paper will review one approach to this problem, the use of switched-capacitor techniques. The paper emphasizes the practical aspects of switched-capacitor filter design under the constraints imposed by MOS integrated-circuit technology. The basic operation of switched-capacitor filters is reviewed, followed by a discussion of the properties of the various circuit building blocks in MOS technology. Finally, a summary of several filter organizations which appear to be well suited to switched-capacitor implementation is presented.     

Stability test for switched-capacitor filters

A general stability test is described which may be employed in the analysis of all switched-capacitor filters of the lossless discrete integrator (LDI) type.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

Parasitics-compensated building blocks for switched-capacitor filters

A switched-capacitor voltage-controlled charge source with differential outputs and a switched-capacitor differential integrator are proposed. The proposed circuits are parasitics insensitive, and can be operated using only a two-phase clock.     

New switched-capacitor ladder filters

A method is described and implemented for the derivation of switched-capacitor discrete-time filters from analogue passive filters of the ladder doubly terminated kind. The method is based on linear transformation active (LTA) synthesis, and yields some very interesting results.     

Pseudopower in switched-capacitor filters

The concepts of pseudopower, pseudopassivity, and pseudolosslessness are introduced in connection with switched-capacitor filters employing voltage invertor switches. With such concepts the verification of the low sensitivity and stability properties is straightforward.     

Sequential voltage-inversion principle for switched-capacitor filters

For a special class of switched-capacitor filters, voltage-inverter switches are needed. It is shown how several voltage-inverter switches can be realised using only one operational amplifier.     

Biquad alternatives for high-frequency switched-capacitor filters

Biquad sections are the basic building block of practical switched-capacitor (SC) filters. The authors focus on the amenability of various biquad options for high-frequency operation. A comparison on the basis of analysis and a recent nonideal SC network simulation tool are confirmed by results from a VLSI 1.25-/spl mu/m CMOS test chip. A differencing-input SC biquad is shown to have a significant performance advantage over other circuits.     

Offset-compensated switched-capacitor leapfrog filters

Offset-compensated SC leapfrog filters can be realised as shown in the letter. The filters are parasitic-insensitive and the switches are controlled by a 3-phase clock. A 5th-order lowpass filter is given as an example.     

Parasitics-insensitive switched-capacitor ladder filters

A simple method for designing parasitics-insensitive switched-capacitor (s.c.) ladder filters is described. The response of the s.c. filter is related to that of a continuous-time prototype circuit by the bilinear z-transform.     

Two port adaptor for wave digital filters based on nonredundantradix-4 arithmetic

Wave digital filters synthesised from two port adaptors are highly recursive structures and hence for high speed implementations it is essential to reduce the latency of the adaptor. This is directly related to the number of addition levels used. Nonredundant radix-4 arithmetic has already been shown to nearly halve the number of levels compared with an uncoded multiplication with much less hardware overhead than the modified Booth algorithm. Nonredundant radix-4 arithmetic is applied to the two-port adaptor. The results compare favourably with previous approaches for most coefficient wordlengths of practical interest     

Canonic ladder realizations of IIR digital filters

Two new canonic realizations of IIR digital filters age presented. The realizations are derived employing modified continued fraction expansion procedures. Proposed methods also provide alternate derivations to the digital lattice and ladder structures based on two-pair extractions and orthogonal polynomial expansions.     

High-frequency CMOS switched-capacitor filters for communications application

Bandpass filters for communications applications are realized using an 80 MHz differential single-stage CMOS operational amplifier and a fully differential identical-resonator elliptic bandpass ladder filter configuration. Experimental results are given for a CMOS sixth-order 260 kHz elliptic bandpass filter with a Q-factor of 40, a clock frequency of 4 MHz, and a power dissipation of 70 mW.     

Improved circuit elements for switched-capacitor ladder filters

A new switched-capacitor floating inductance simulation circuit which does not depend on matching of passive elements is presented. A switched-capacitor source termination circuit which functions as a sample-and-hold circuit for a filter is also described.     

Compensation for parasitic capacitances in switched-capacitor filters

Three methods are described for eliminating the effects of parasitic capacitances associated with floating capacitors in switched-capacitor filters.     

CMOS switched-capacitor filters for a PCM voice CODEC

Three switched-capacitor circuits are described which perform all filtering functions in a PCM voice CODEC. They use novel integrators and/or state-variable sections, which desensitize the overall response against stray-capacitance effects. All filters are fully integrated on a CMOS test chip. The basic design considerations and the measured performance are discussed.     

CMOS high-frequency switched-capacitor filters fortelecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f_s =2f_clock=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f_c) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f _c, and -30 dB at 1.25 f_c. For the 12-MHz corner frequency setting, given the 2V_pp differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-μm 5-V (0.48 μm drawn) CMOS process     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off-and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.