共查询到18条相似文献,搜索用时 46 毫秒
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通过采用结构力学的力法,建立了求解叉指式微结构加速度传感器刚度的力学模型,并得到了精确解。与材料力学方法相比,该模型推导过程简单;与有限元方法相比,该模型在同等力学假设的条件,精度更高,且将计算分析的工作效率大大提高。 相似文献
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微硅隧道加速度传感器设计 总被引:2,自引:0,他引:2
比较了压阻式、电容式和隧道式加速度传感器的特点 ,提出了扭摆式隧道加速度传感器的结构 ,给出了工作原理和设计模型 ,最后给出了结构尺寸、版图总图及试制的芯片照片。 相似文献
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本文介绍了一种新结构的硅一体化微加速度传感器,理论和实验结果表明,这种传感器与传统硅微机械结构加速度传感器相经具有温度特性好,工艺简单和成品率高等优点,这种结构特别适合制作谐振传感器。 相似文献
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以角锥棱镜作为惯性元件,利用光学干涉原理,可以实现对运动物体的二维加速度测量。本文给出了二维加速度激光传感器的设计理论和测量原理。 相似文献
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分析了影响加速度计分辨率的因素,在此基础上,通过采用深度反应离子刻蚀工艺获得大的敏感质量和小的电极间隙、采用电容变化量比枝齿梳状敏感结构大一倍的直齿梳状敏感结构和利用静电负刚度来降低结构的刚度等措施提高器件分辨率。最后给出了一种新的设计方案,叙述了其工作原理并分析了影响其闭环灵敏度的因素。 相似文献
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This paper reports a high-sensitivity low-noise capacitive accelerometer system with one micro-g//spl radic/Hz resolution. The accelerometer and interface electronics together operate as a second-order electromechanical sigma-delta modulator. A detailed noise analysis of electromechanical sigma-delta capacitive accelerometers with a final goal of achieving sub-/spl mu/g resolution is also presented. The analysis and test results have shown that amplifier thermal and sensor charging reference voltage noises are dominant in open-loop mode of operation. For closed-loop mode of operation, mass-residual motion is the dominant noise source at low sampling frequencies. By increasing the sampling frequency, both open-loop and closed-loop overall noise can be reduced significantly. The interface circuit has more than 120 dB dynamic range and can resolve better than 10 aF. The complete module operates from a single 5-V supply and has a measured sensitivity of 960 mV/g with a noise floor of 1.08 /spl mu/g//spl radic/Hz in open-loop. This system can resolve better than 10 /spl mu/g//spl radic/Hz in closed-loop. 相似文献
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A low-voltage tunneling-based silicon microaccelerometer 总被引:6,自引:0,他引:6
This paper describes the design, fabrication, and testing of a low-voltage tunneling-based silicon microaccelerometer. The device has been successfully batch-fabricated by the boron etch-stop dissolved wafer process. A 4 h, 1100°C oxygen, post-diffusion annealing process has been developed to eliminate the stress gradient in and warpage of thin (≈3 μm) heavily-boron-doped silicon microstructures. Using a simple discrete readout circuit, the device with an active area of 400×400 μm2 provides a measured sensitivity of 1.66×104 ppm/g (133 mV/g), bandwidth of 2 kHz in air, and a full scale range of 30 g with a nonlinearity of 0.6%. The measured noise spectrum exhibits a typical 1/f behavior and drops from 1.75 mg/√Hz (at 50 Hz) to 0.25 mg/√Hz (at 2 kHz), corresponding to a minimum detectable acceleration of 22.8 mg. The variations of the offset output voltage and device sensitivity are ±40 mV (≈0.5%) and ±0.65 mV/g (≈0.49%) in continuous operation over thirty days. The temperature coefficient of offset (TCO) and temperature coefficient of sensitivity (TCS) are -600 ppm/°C and 1200 ppm/°C, respectively 相似文献
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Chung-Yu Wu Chin-Fong Chiu 《Solid-State Circuits, IEEE Journal of》1995,30(8):890-897
A new silicon retina is proposed to realize the functions of the vertebrate retina. In the proposed silicon retina, each basic cell consists of two separated bipolar phototransistors only. The smooth function of the horizontal cell in the vertebrate retina is efficiently achieved by the diffusion and redistribution of the photogenerated excess carriers in the common base region of the phototransistors. Thus, the structure of the new silicon retina is very simple and compact. It can be easily implemented in both CMOS and BiCMOS technologies with a small chip area. A 2-D array of 32*32 new silicon retina cells has been designed and fabricated in 0.8 μm N-well CMOS process. Experimental results show that the new silicon retina is capable of extracting the edge of the image and detecting the moving object 相似文献
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Porous silicon for the development of capacitive microstructures 总被引:1,自引:0,他引:1
Macroporous silicon is developed in p-type substrates in order to extend the active surface area of the electrodes in a silicon integrated capacitive element. Some laboratory prototypes with a 3D architecture and Si/SiO2/PolySi layers have been developed. The contribution of the surface enlargement to the final capacitance is analyzed by comparing it with a 2D planar reference capacitive device. By this method, a capacitance gain of 2400% has been obtained at low frequencies with a capacitance density of 180 nF/cm2. Based on the physical microstructure, an equivalent electrical circuit of the porous capacitive element is proposed and its electrical behavior discussed. 相似文献
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A novel capacitive microaccelerometer is designed which can operate reliably under high load. The movable structure of the microaccelerometer is a stepped circular plate which is fully compliant. Touch mode is introduced into the microaccelerometer, and small-area touch mode as a novel touch mode for MEMS is developed without the use of dielectric layer. A switch electrode is located on the substrate to prevent the short circuit of variable capacitor’s electrodes. Accurate, time saving and memory space saving models are developed with a new numerical method and validated with finite element method and boundary element method. Electrostatic force is taken into account, so the touch analysis includes an electromechanical coupling analysis. Internal mechanical force such as thermal stress and residual stress which will induce abnormal operation also is taken into account. The novel microaccelerometer’s performance is analyzed, verifying the device’s reliability, verifying the developed models’ availability for performance analysis over full measurement range. 相似文献
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We have developed a novel batch-fabrication single-crystalline silicon micromirror bonding process to fabricate optically flat micromirrors on polysilicon surface-micromachined two-dimensional (2-D) scanners. The electrostatically actuated 2-D scanner has a mirror area of 460 μm×460 μm and an optical scan angle of ±7.5°. Compared with micromirror made by standard polysilicon surface-micromachining process, the radius of curvature of the micromirror has been improved by 150 times from 1.8 to 265 cm, with surface roughness <10 nm 相似文献