Digital characteristics of CMOS devices at cryogenic temperatures

The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V_II and V_IH increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V _H-V_I, and V_IH-V _II all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β_N/β_P ratio as the temperature is lowered     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

Experimental determination of self-heating in submicrometer MOStransistors operated in a liquid-helium ambient

Self-heating (SH) in submicrometer CMOS transistors operated at liquid-helium temperature and under different bias conditions was experimentally verified by measuring the temperature T_Si in the proximity of the device. T_Si was measured by using a silicon resistor, placed in the same bulk nearby the device under test, as a temperature sensor. It was found that the heat generated by the NMOS transistor of a CMOS inverter structure penetrates deep into the substrate and reduces very strongly the n-well impedance, giving rise to large variations in the kink of the I_drain -V_drain characteristics of the neighbor PMOS transistor. Experimental results confirm that SH must not be underestimated when characterizing and modeling low-temperature device operation     

A latch phenomenon in buried N-body SOI NMOSFET's

The authors show that a snapback effect resulting in a latching can exist in a buried N-body NMOS device on silicon-on-insulator (SOI). Using numerical simulations, it is demonstrated that when V_GS is less than the flat-band voltage and after triggering, this kind of device behaves as a floating-base n-p-n bipolar transistor, the base hole density of which is controlled by an inversion layer instead of the usual base doping. The latch phenomenon results from the combination of this parasitic quasi-bipolar device, a back surface NMOS transistor, and impact ionization current     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

The effect of substrate bias on hot-carrier damage in NMOS devices

Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V_d =8 V and V_g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V_b), having a power-law gradient of 0.5 for V_b=0 V and 0.3 for V_b=-9 V. Investigation of the type of damage resulting from stressing shows that at V_b=0 V, interface state generation results, while at V_b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

A latch-up-like new failure mechanism for high-density CMOS dynamicRAMs

A latch-up-like failure phenomenon that shows hysteresis in the V_cc-I_cc characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor     

Current-crowding effect in diagonal MOSFET's

Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I_sub condition (V_g =0.5 V_d). However, in the high-gate-bias region (V_g=V_d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I_sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V_g>V_d), this current-crowding effect in the diagonal transistor can be a serious reliability concern     

Minimizing floating-body-induced threshold voltage variation inpartially depleted SOI CMOS

Pulse propagation problems associated with dynamic floating-body effects, e.g., pulse stretching, is measured in partially depleted SOI CMOS inverter chains. Pulse stretching is found to be dependent on pulse frequency and V_DD. Such behavior is attributed to floating-body-induced transient threshold voltage variation in partially depleted SOI CMOS devices due to floating-body charge imbalance between logic states during CMOS switching. Such an imbalance can be minimized through proper device design because of the different dependencies of the gate and drain depletion charges on channel length, silicon film thickness, gate oxide thickness, channel doping, and supply voltage. This is confirmed by measuring the maximum transient threshold voltage variation in discrete partially depleted SOI NMOS devices in configurations which are predictive of CMOS switching behavior     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

Doubly strainedIn0.41Al0.59As/n+-In0.65Ga0.35As HFET with high breakdown voltage

An In_0.41Al_0.59As/n⁺-In_0.65 Ga_0.35As HFET on InP was designed and fabricated, using the following methodology to enhance device breakdown: a quantum-well channel to introduce electron quantization and increase the effective channel bandgap, a strained In_0.41Al_0.59As insulator, and the elimination of parasitic mesa-sidewall gate leakage. The In_0.65Ga_0.35As channel is optimally doped to N_D=6×10¹⁸ cm^-3. The resulting device (L_g=1.9 μm, W_g =200 μm) has f_t=14.9 GHz, f_max in the range of 85 to 101 GHz, MSG=17.6 dB at 12 GHz V_B=12.8 V, and I_D(max)=302 mA/mm. This structure offers the promise of high-voltage applications at high frequencies on InP     

Modeling hot-carrier effects in polysilicon emitter bipolartransistors

In self-aligned polysilicon emitter transistors a large electric field existing at the periphery of the emitter-base junction under reverse bias can create hot-carrier-induced degradation. The degradation of polysilicon emitter transistor gain under DC stress conditions can be modelled by ΔI_B∝I_R ^m+ntⁿ where n≈0.5 and m ≈0.5. The more complex relationships of Δβ(I _C, I_R, t) and β(I _C, I_R, t) result naturally from the simple ΔI_B model. Using these relationships the device lifetime can be extrapolated over a wide range of reverse stress currents for a given technology     

Negative base current and impact ionization phenomena inAlGaAs/GaAs HBTs

Impact ionization phenomena in the collector region of AlGaAs/GaAs heterojunction bipolar transistors give rise to base current reduction and reversal. These phenomena can be characterized by extracting the M-1 coefficient, which can be evaluated by measuring base current changes. Measurements of M-1 are affected at low current densities by the presence of the collector-base junction reverse current I_CBO. At high current densities, three effects contribute to lower the measured M-1 value: voltage drops due to collector (R_C) and base (R_B) parasitic resistances, device self-heating, and lowering of the base-collector junction electric field due to mobile carriers. By appropriately choosing the emitter current value, parasitic phenomena are avoided and the behavior of M-1 as a function of the collector-base voltage V_CB in AlGaAs/GaAs HBTs is accurately characterized     

Low-frequency noise characteristics of lattice-matched(x=0.53) and strained (x>0.53) In0.52Al0.48As/InxGa1-xAs HEMT's

Extensive bias-dependent and temperature-dependent low-frequency (LF) noise measurements were performed on lattice-matched and strained In_0.52Al_0.48As/In_xGa_1-x As(0.53<x<0.70) HEMTs. The input-noise voltage spectra density is insensitive to V_DS bias and shows a minimum at V_GS corresponding to the peak g_m condition. The corresponding output-noise voltage spectral density, which depends strongly on the gain of the devices, increases with V_DS. The input noise was rather insensitive to indium (In) content. Temperature-dependent low-frequency noise measurements on these devices reveal shallow traps with energies of 0.11, 0.15, and 0.18 eV for 60%, 65%, and 70% In HEMTs. Noise transition frequencies for these devices were on the order of 200-300 MHz and remain almost the same for different channel In content and V_DS bias     

Extraction of DC base parasitic resistance of bipolar transistorsbased on impact-ionization-induced base current reversal

A method for the evaluation of the DC base parasitic resistance, R_B, of bipolar transistors is described. The method is based on impact-ionization-induced base current reversal and enables R_B to be evaluated independently from the emitter parasitic resistance in a wide range of emitter current and collector-base voltage, without requiring any special device structure. The method can also extract R_B in the impact-ionization regime, where current crowding due to negative base current induces an increase in R_B at increasing emitter current     

The effect of channel hot-carrier stressing on gate-oxide integrityin MOSFETs

The correlation between channel hot-carrier stressing and gate-oxide integrity is studied. It is found that channel hot carriers have no detectable effect on gate-oxide integrity even when other parameters (e.g., ΔV_T and ΔI _D) have become intolerably degraded. In the extreme cases of stressing at V_G≈V_T with measurable hole injection current, however, the oxide charge to breakdown decreases linearly with the amount of hole fluence injected during the channel hot-hole stressing. This may limit the endurance of a nonvolatile memory using hot holes for erasing. This can also explain the gate-to-drain breakdown of a device biased in the snap-back region, since snap-back at low gate voltage is favorable for hole injection. Snap-back-induced oxide breakdown could be an ESD (electrostatic discharge) failure mechanism     

A simple characterization method for silicon-on-insulator materialsusing a depletion-mode MOSFET

A simple method is proposed for extracting the electrical parameters of a silicon-on-insulator (SOI) material from a depletion-mode MOSFET. It is based on an analysis of static input current-voltage I_D(V_G) and transconductance-voltage g_m(V_G) characteristics in the linear region. Functions varying linearly with gate voltage are constructed from I_D(V_G) and g_m(V_G) functions. These new functions allow a straightforward determination of the parameters usually obtained from a capacitance-voltage measurement (doping level, oxide charge, etc.) and also the bulk-layer and accumulation-layer carrier mobility     

Gate-controlled negative differential resistance in drain currentcharacteristics of AlGaAs/InGaAs/GaAs pseudomorphic MODFETs

The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L _g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V_ds>2.5 V and V_gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V_gs<0 V resulting in f_max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V_gs >0 V and V_ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions