Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

n-Channel Si-gate process for MNOS EEPROM transistors

An n-channel Si-gate process has been developed to fabricate MNOS EEPROM transistors and fast logic circuits on one chip. The technology proposed involves low thermal oxidation temperatures ≤900°C after nitride deposition, two LOCOS process steps and application of self-aligned overlapped poly-Si contacts. The MNOS memory transistors obtained have been programmed by ±25 V pulses with a write time of t_w = 10 ms and an erase time of t_e = 100 ms.The retention data have been found to be dependent on nitride thickness and threshold voltage shift, but independent of channel length and channel doping. For devices with a nitride thickness of 30.5 nm the short-term decay rate of 0.6 V/(decade of time) has been determined. Endurance testing using up to 10⁷ pulses of ±25 V, 100 μs corresponding to approx. 10⁴ write/erase cycles showed no time dependence for the decay rate over the time of 10⁵ min in which retention measurements were made.     

FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device

The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor with a floating gate. The p⁺regions are placed outside the channel area by aligning them with the floating gate and are adjacent to the diffused n⁺source and/or drain regions. This device can operate in the write/erase modes under low-voltage (12 V) and high-speed (< 1 ms) conditions using only a pair of positive pulses. This is achieved with a novel avalanche transition at the channel corner through a relatively thin (4-6 nm thick) oxide under the open-drain condition.     

Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 /spl mu/m and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180/spl mu/m2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of /spl plusmn/1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10/sup 4/ write/erase cycles.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

A 1 Mb EEPROM with MONOS memory cell for semiconductor diskapplication

A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of ±9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 μm² with 1.2 μm lithography, and the die size of the fabricated chip is 5.3 mm×6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 μs/B equivalent (140 ms/chip) was obtained     

A new memory element based on silicon nanoclusters in a ZrO<Subscript>2</Subscript> insulator with a high permittivity for electrically erasable read-only memory

The write and erase function and the data retention characteristics of a memory element designed to be used in electrically erasable read-only memory and based on a silicon-oxide-(silicon dot)-oxide-polysilicon structure, in which either a SiO₂ insulator or a ZrO₂ high-permittivity insulator are used as blocking oxides, are simulated. It is established that the use of the high-permittivity insulator gives rise to a number of effects: spurious injection from poly-Si is reduced; the electric field in the tunneling oxide increases; it becomes possible to increase the thickness of the tunneling insulator and, consequently, to increase the data retention time; and lower voltages for the write and erase functions can be used. Programming with a pulse of ±11 V possessing a width of 10 ms makes it possible to retain a memory window of ～3 V for 10 years.     

Non-volatile memory based on silicon nanoclusters

Write/erase and charge retention characteristics of a memory element for the electrically programmable read-only memory based on the silicon/oxide_l/oxide_2/silicon_dot/oxide/semiconductor structure were simulated. An alternative high-κ dielectric (ZrO₂) was used as a blocking oxide and the second tunnel oxide. A thin low-κ dielectric (SiO₂) was used as the first tunneling oxide. Due to such a configuration, injection characteristics of tunneling SiO₂ in the write/erase mode can be significantly improved; hence, the response rate and injected charge can be increased. At the same time, the use of the sufficiently thick blocking and second tunneling layers allows injected charge retention for a long time. Programming by a pulse 10 ms long with an amplitude of ±11 V makes it possible to obtain a memory window of ～6 V in 10 years.     

Characterization of scaled MANOS nonvolatile semiconductor memory (NVSM) devices

We have modeled and characterized scaled Metal–Al₂O₃–Nitride–Oxide–Silicon (MANOS) nonvolatile semiconductor memory (NVSM) devices. The MANOS NVSM transistors are fabricated with a high-K (K_A = 9) blocking insulator of ALD deposited Al₂O₃ (8 nm), a LPCVD silicon nitride film (8 nm) for charge-storage, and a thermally grown tunneling oxide (2.2 nm). A low voltage program (+8 V, 30 μs) and erase (?8 V, 100 ms) provides an initial memory window of 2.7 V and a 1.4 V window at 10 years for an extracted nitride trap density of 6 × 10¹⁸ traps/cm³ eV. The devices show excellent endurance with no memory window degradation to 10⁶ write/erase cycles. We have developed a pulse response model of write/erase operations for SONOS-type NVSMs. In this model, we consider the major charge transport mechanisms are band-to-band tunneling and/or trap-assisted tunneling. Electron injection from the inversion layer is treated as the dominant carrier injection for the write operation, while hole injection from the substrate and electron injection from the gate electrode are employed in the erase operation. Meanwhile, electron back tunneling is needed to explain the erase slope of the MANOS devices at low erase voltage operation. Using a numerical method, the pulse response of the threshold voltages is simulated in good agreement with experimental data. In addition, we apply this model to advanced commercial TANOS devices.     

Improving radiation hardness of EEPROM/flash cell by N2Oannealing

The effects of an N₂O anneal on the radiation effects of a split-gate electrical erasable programmable read only memory (EEPROM)/flash cell with a recently-proposed horn-shaped floating gate were studied. We have found that although the cells appear to survive 1 Mrad(Si) Co⁶⁰ irradiation without data retention failure, the write/erase cycling endurance was severely impeded after irradiation. Specifically, the write/erase cycling endurance was degraded to 20 K from the pre-irradiation value of 50 K. However, by adding an N₂ O annealing step after the interpoly oxidation, the after-irradiation write/erase cycling endurance of the resultant cell can be significantly improved to over 45 K. N₂O annealing also improves the after-irradiation program and erase efficiencies. The N₂O annealing step therefore presents a potential method for enhancing the robustness of the horn-shaped floating-gate EEPROM/flash cells for radiation-hard applications     

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm², a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 10⁴write/erase cycles.     

BE-TANOS: Feasibility and technology limitations

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO₂-Si₃N₄-SiO₂ stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.     

A nonvolatile charge-addressed memory (NOVCAM) cell

A nonvolatile charge-addressed memory (NOVCAM) cell is described in a 64-bit shift register configuration. The charge address is performed by a charge-coupled device (CCD) shift register and the information is stored in metal-nitride-oxide-silicon (MNOS) nonvolatile sites located in parallel with the CCD shift register. The tunneling electric field strength across the thin-oxide MNOS structure is controlled by the magnitude of the charge transferred from the CCD register. The write, erase, and read modes of operation are discussed with typical /spl plusmn/20 V 10 /spl mu/s write/erase, and 2 V 2 /spl mu/s read conditions. Readout is accomplished by parallel stabilized charge injection from a diffused p/n junction to minimize access time to the first bit.     

Nanocrystal Memory Cell Integration in a Stand-Alone 16-Mb nor Flash Device

We report on the full process integration of nanocrystal (NC) memory cells in a stand-alone 16-Mb NOR Flash device. The Si NCs are deposited by chemical vapor deposition on a thin tunnel oxide, whose surface is treated with a low thermal budget process, which increases NC density and minimizes oxide degradation. The device fabrication has been obtained by means of conventional Flash technology, which is integrated with the CMOS periphery with high- and low-voltage transistors and charge pump capacitors. The memory program and erase threshold voltage distributions are well separated and narrow. The voltage distribution widths are related to NC sizes and dispersion, and bigger NCs can induce a cell reliability weakness. An endurance issue is also related to the use of an oxide/nitride/oxide dielectric which acts as a charge trapping layer, causing a shift in the program/erase window and a distribution broadening during cycling.     

A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing together with thin-oxide technology, and has an area of 24 × 24 µm2using 4-µm design rules. The cell is of the floating gate type, and employs avalanche injection of electrons and holes from a common injector. The use of thin oxide (≃ 100 Å) between the n⁺-p⁺injector region of the substrate and the floating gate of the memory transistor makes operation possible using voltages of less than 20 V. Write and erase times are 10 ms with an endurance to write-erase cycling of 10⁵cycles. The power dissipation during writing and erasing is 10 mW.     

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively     

Endurance of thin-oxide nonvolatile MNOS memory transistors

A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si3N4dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 10¹⁰erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time.     

A novel PHINES flash memory cell with low power program/erase, small pitch, two-bits-per-cell for data storage applications

A novel programming by hot-hole injection nitride electron storage (PHINES) Flash memory technology is developed. The memory bit size of 0.046 /spl mu/m/sup 2/ is fabricated based on 0.13-/spl mu/m technology. PHINES cell uses a nitride trapping storage cell structure. Fowler-Nordheim (FN) injection is performed to raise V/sub t/ in erase while programming is done by lowering a local V/sub t/ through band-to-band tunneling-induced hot hole (BTBT HH) injection. Two-bits-per-cell feasibility, low-power and high-speed program/erase, good endurance and data retentivity make it a promising candidate for Flash EEPROM technology in gigabit era applications.     

A novel P-channel nitride-trapping nonvolatile memory device with excellent reliability properties

A novel P-channel nitride trapping nonvolatile memory device is studied. The device uses a P/sup +/-poly gate to reduce gate injection during channel erase, and a relatively thick tunnel oxide (>5 nm) to prevent charge loss. The programming is carried out by low-power band-to-band tunneling induced hot-electron (BTBTHE) injection. For the erase, self-convergent channel erase is used to expel the electrons out of nitride. Experimental results show that this p-channel device is immune to read disturb due to the large potential barrier for hole tunneling. Excellent P/E cycling endurance and retention properties are demonstrated. This p-channel device shows potential for high-density NAND-type array application with high-programming throughput (>10 Mb/sec).