总剂量辐照对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65 nm 体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。     

抗辐射0.18μm NMOS器件热载流子效应研究

基于0.18μm CMOS工艺开发了抗总剂量辐射加固技术,制备的1.8 V NMOS器件常态性能良好,器件在500 krad(Si)剂量点时,阈值电压与关态漏电流无明显变化。研究器件的热载流子效应,采用体电流Isub/漏电流Id模型评估器件的HCI寿命,寿命达到5.75年,满足在1.1 Vdd电压下工作寿命大于0.2年的规范要求。探索总剂量辐射效应与热载流子效应的耦合作用,对比辐照与非辐照器件的热载流子损伤,器件经辐照并退火后,受到的热载流子影响变弱。评估加固工艺对器件HCI可靠性的影响,结果表明场区总剂量加固工艺并不会造成热载流子损伤加剧的问题。     

空间辐射环境下SiC功率MOSFET栅氧长期可靠性研究

利用等效1 MeV中子和γ射线对1200 V SiC功率MOSFET进行辐射,研究了电离损伤和位移损伤对器件的影响,并分析了辐射后器件栅氧长期可靠性。结果表明：中子辐射后器件导通电阻发生明显退化,与辐射引入近界面缺陷降低载流子寿命和载流子迁移率有关。时间依赖的介质击穿(TDDB)结果表明,栅泄漏电流呈现先增加后降低趋势,与空穴捕获和电子捕获效应有关。中子辐射后栅漏电演化形式未改变,但氧化层击穿时间增加,这是中子辐射缺陷增加了Fowler-Nordheim(FN)隧穿势垒的缘故。总剂量辐射在器件氧化层内引入陷阱电荷,使得器件阈值电压负向漂移。随后的TDDB测试表明,与中子辐射一致,总剂量辐射未改变栅漏电演化形式,但氧化层击穿时间提前。这是总剂量辐射在氧化层内引入额外空穴陷阱和中性电子陷阱的缘故。     

典型电子器件中子和总剂量辐照协同损伤研究

研究了几种典型电源类电子器件的中子和总剂量辐射效应,包括单总剂量效应、单中子辐射效应、总剂量和中子分时序贯辐照效应以及中子和总剂量同时辐照效应,分析了不同辐照条件下电子器件的失效中子注量(总剂量)阈值。试验结果显示,分时序贯、同时辐照试验给出的电子器件辐照失效阈值低,而单项辐射效应试验给出的失效阈值偏高。对于该类双极工艺器件存在协同增强损伤的机理进行了分析,其主要原因在于同时辐照时,电离损伤在晶体管氧化层产生氧化物正电荷,使基区表面势增加,与此同时界面态数量增多,减少Si体内次表面载流子浓度的差异,从而使电流增益的退化加剧,增强晶体管的中子位移损伤。按照同时辐照进行试验考核,更能真实评估器件的综合抗辐射性能,研究结果对于器件抗辐射性能评估具有重要意义。     

栅长对深亚微米器件总剂量辐射诱生漏电流的影响研究

对0.18 um 工艺NMOSFET器件进行总剂量辐照实验,包括不同栅长器件。由于深亚微米器件栅氧化层厚度较薄,对总剂量辐照不敏感,辐照前后器件阈值电压基本不发生变化。所有尺寸器件的关态漏电流随总剂量增加而增加。我们认为,总剂量辐射在浅沟槽隔离氧化物侧壁诱生成源漏之间漏电路径。该漏电路径是由于浅沟槽隔离氧化物种陷阱正电荷形成的。研究发现,辐射诱生的漏电流大小与器件栅长密切相关。通过主晶体管和寄生晶体管模型可以很好解释该现象。     

异质栅MOSFET热载流子效应的研究

异质栅MOSFET器件的栅极由具有不同功函数的两种材料拼接而成,能够提高载流子输运速度、抑制阈值电压漂移等.文中比较了异质栅MOSFET和常规MOSFET的热载流子退化特性.通过使用器件数值模拟软件MEDICI,对能有效监测热载流子效应的参数,例如电场、衬底电流和栅电流等参数进行仿真.将仿真结果与常规MOSFET对比,从抑制热载流子效应方面验证了新结构器件的高性能.     

超薄氮氧化硅(Sio_xN_y)栅NMOSFET中GIDL效应的研究

MOSFET栅介质层厚度的减薄使栅致漏极的泄漏（GIDL）电流指数增强，本文报道N2O中退火SiO2（两步法）生成超薄（5．5nm）氮氧化硅（SiOxNy）栅NMOSFET中的GIDL效应，包括器件尺寸、偏置电压和热载流子效应的影响．发现GIDL在一定的偏置下成为主要的泄漏机制，且陷阱电荷和界面态对其具有显著的调制作用．二维器件模拟结果指出，与SiO2栅NMOSFET相比，LDD掺杂结构使SiOxNy栅NMOSFET的GIDL进一步增强．     

超深亚微米SOI总剂量效应泄漏电流模型

总剂量辐射效应会导致绝缘体上硅金属氧化物半导体场效应晶体管(SOI MOSFET)器件的阈值电压漂移、泄漏电流增大等退化特性。浅沟槽隔离(STI)漏电是器件退化的主要因素,会形成漏极到源极的寄生晶体管。针对130 nm部分耗尽(PD) SOI NMOSFET器件的总剂量辐射退化特性,建立了一个包含总剂量辐射效应的通用模拟电路仿真器(SPICE)模型。在BSIM SOI标准工艺集约模型的基础上,增加了STI寄生晶体管泄漏电流模型,并考虑了辐射陷阱电荷引起寄生晶体管的等效栅宽和栅氧厚度的变化。通过与不同漏压下、不同宽长比的器件退化特性的实验结果对比,该模型能够准确反映器件辐射前后的漏电流特性变化,为器件的抗辐射设计提供参考依据。     

AlGaN/GaN HEMT泄漏电流的退化研究

针对AlGaN/GaN HEMT器件在寿命试验过程中经常出现的栅源、栅漏和源漏泄漏电流随试验时间的延长而增大的现象,展开了深入的研究.分析了当前HEMT器件泄漏电流的各种主流退化模型,通过试验发现热载流子效应、逆压电效应等难以完全解释泄漏电流间的退化差异.进一步的研究显示,电极间的泄漏电流的差异主要是由材料中的缺陷和陷阱的密度分布不均匀造成的.在应力的作用下,初始密度越大,试验过程中缺陷和陷阱的增长速度就越快,泄漏电流的增长速度也就越快.但应力撤除后,由陷阱辅助隧穿导致的泄露电流会逐渐地得到恢复.     

高压LDMOS准饱和效应研究

借助于SILVACO TCAD仿真工具,研究了高压LDMOS电流准饱和效应(Quasi-saturation effect)的形成原因。通过分析不同栅极电压下漂移区的耗尽情况以及沟道与漂移区电势、电场和载流子漂移速度的分布变化,认为当栅压较低时,LDMOS的本征MOSFET工作在饱和区,栅压对源漏电流的钳制明显,此时沟道载流子速度饱和;而在大栅压下,随着沟道导电能力的增加以及漂移区两端承载的电压的增大,本征MOSFET两端压降迅速降低,器件不能稳定地工作在饱和区而进入线性工作区,此时沟道中的载流子速度不饱和。LDMOS器件的源漏电流的增大主要受漂移区影响,栅压逐渐失去对器件电流的控制,此时增大栅压LDMOS器件的源漏电流变化很少,形成源漏电流的准饱和效应。最后,从器件工作过程对电流与栅压的关系进行了理论分析,并从理论结果对电流准饱和效应进行了深入分析。     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对pMOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于pMOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是pMOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

Degradation induced by TID radiation and hot-carrier stress in 130-nm short channel PDSOI NMOSFETs

Hot-carrier reliability for devices operating in radiation environment must be considered. In this paper, we investigate how total ionizing dose impacts the hot-carrier reliability of partially-depleted SOI I/O NMOSFETs, highlighting the effect of buried oxide. Firstly, radiation-induced damage on short channel SOI devices with 100 nm thick Si film was investigated. After low total dose irradiation, incomplete fully-depleted state has been formed due to the non-uniformly distributed positive charges in the buried oxide. Furthermore, as the dominated factor of hot-carrier injection, the body current reduces after irradiation. Subsequently, the irradiated SOI devices were subjected to hot-carrier stress for 9000-s long time. Compared with unirradiated devices, the irradiated samples display enhanced hot-carrier degradation. We attribute this phenomenon to that radiation lowers the barrier for hot-carrier injection. Therefore, in order to ensure the reliability of SOI devices operating in harsh radiation environments, SOI devices with higher quality or corresponding hardness design should be taken.     

一种用于分离pMOS器件热载流子应力下氧化层陷阱电荷和界面陷阱电荷对阈值电压退化作用的方法

在电荷泵技术的基础上,提出了一种新的方法用于分离和确定氧化层陷阱电荷和界面陷阱电荷对p MOS器件热载流子应力下的阈值电压退化的作用,并且这种方法得到了实验的验证.结果表明对于p MOS器件退化存在三种机制:电子陷阱俘获、空穴陷阱俘获和界面陷阱产生.需要注意的是界面陷阱产生仍然是p MOS器件热载流子退化的主要机制,不过氧化层陷阱电荷的作用也不可忽视.     

X-ray lithography induced radiation damage in CMOS and bipolar devices

Radiation effects from a synchroton x-ray lithography source on the performance degradation and long term reliability of high performance self-aligned bipolar devices and deep sub-micron CMOS devices are studied. The hot-carrier properties of the x-ray induced damage in CMOS devices, such as interface states, positive oxide charges and neutral traps have been examined. The effect of these radiation induced defects and their impact on the DRAM circuits in terms of the performance and reliability are discussed. In the self-aligned, double polysilicon bipolar transistor structure interface states and trapped charges can be generated by the radiation source in the sidewall oxide near the emitter-base junction such damage can increase the emitter-base leakage current. This increase of base current can substantially degrade the device current gain at low bias.     

Synchrotron x-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm².     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

Effect of mobile charge on hot-carrier degradation in lateral diffused MOSFET

Hot carrier-induced device degradation in n-type lateral diffused MOSFETs with mobile charges in gate oxide has been studied. Abnormal decrease-then-increase in V/sub th/ during hot-carrier stress was observed. The decrease was found to be caused by movement of mobile charges while the increase was the normally observed hot-electron degradation. The hot-electron degradation was drastically accelerated with the presence of mobile charges and easily recovered after baking or negative gate bias. The magnitude of degradation linearly increases with mobile charge density. The acceptable limits of mobile charge density have been estimated. The observed behaviors are very similar to positive charging processes found in other n-MOSFETs that were attributed to hot-hole effects, suggesting mobile charge induced degradation must be carefully excluded in hot-hole injection studies.     

Analytical modelling of electrical characteristics in γ-irradiated power VDMOS transistors

This paper deals with an analysis of γ-irradiation effects on basic electrical characteristics of power VDMOS transistors operated in both linear and saturation regions. First, an analytical model that yields the drain current and transconductance dependencies on gate oxide charge density is developed. The experimental data are utilized to establish a direct relation between the absorbed irradiation dose and the corresponding effective density of gate oxide charges. The drain current and transconductance of VDMOS devices are then modelled as the functions of radiation dose. Finally, the results of modelling are compared with experimental data.     

A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.