一种CMOS工艺离子敏场效应型晶体管的模型

采用CMOS工艺可以实现离子敏场效应型晶体管(ISFET),若在栅极氧化层之上保留多晶硅层,并通过引线使其与 外界的金属层相连作为悬浮的栅极,可实现悬浮栅结构ISFET.从ISFET的传感机理出发,根据表面基模型,利用HSPICE建 立了悬浮栅结构ISFET的物理模型.以该模型为研究对象,探讨了薄膜等效电阻、薄膜等效电...     

Transformerless capacitive coupling of gate signals for seriesoperation of power MOS devices

A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each metal oxide semiconductor field effect transistor (MOSFET), except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage division across the network of device capacitance and inserted capacitances triggers the entire series stack reliably. Design formulas are presented and simple circuit protection is discussed. Simulation shows reliable operation and experimental verification is presented, Application of the method is applied to series insulated gate bipolar transistors (IGBTs)     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

纳米金属-氧化物-半导体场效应晶体管的热电子发射和弹道输运模型

本文首先给出了SOI上纳米金属-氧化物-半导体场效应晶体管(NANO-MOSFET)的结构,它是一种非传统MOSFET.NANO-MOSFET源漏区采用金属,沟道采用本征硅,该结构避免了传统MOSFET的短沟道效应.利用一组基本器件方程式,我们模拟并分析了 NANO-MOSFET的基本特性.计算表明,NANO-MOSFET在一定范围内源漏电导受栅极电压显著调控,适用于各种数字电路,包括存储单元.另外,选取合适的直流偏置点,NANO-MOSFET可用作模拟小信号放大器.     

Simplified ohmic and Schottky contact formation for field effecttransistors using the single layer integrated metal field effecttransistor (SLIMFET) process

A new III-V semiconductor device fabrication process for GaAs-based field effect transistors (FET) is presented which uses a single lithographic process and metal deposition step to form both the ohmic drain/source contacts and the Schottky gate contact concurrently. This single layer integrated metal FET (SLIMFET) process simplifies the fabrication process by eliminating an additional lithographic step for gate definition, a separate gate metallization step, and thermal annealing for ohmic contact formation. The SLIMFET process requires a FET structure which incorporates a compositionally graded In_xGa_1-xAs cap layer to form low resistance, nonalloyed ohmic contacts using standard Schottky metals. The SLIMFET process also uses a Si₃N₄ mask to provide selective removal of the InGaAs ohmic layers from the gate region prior to metallization without requiring an additional lithographic step. GaAs MESFET devices were fabricated using this new SLIMFET process which achieved DC and RF performance comparable to GaAs MESFET's fabricated by conventional methods     

Ultra‐Low‐Power Differential ISFET/REFET Readout Circuit

A novel ultra‐low‐power readout circuit for a pH‐sensitive ion‐sensitive field‐effect transistor (ISFET) is proposed. It uses an ISFET/reference FET (REFET) differential pair operating in weak‐inversion and a simple current‐mode metal‐oxide semiconductor FET (MOSFET) translinear circuit. Simulation results verify that the circuit operates with excellent common‐mode rejection ability and good linearity for a single pH range from 4 to 10, while only 4 nA is drawn from a single 1 V supply voltage.     

离子敏感场效应晶体管传感器研究进展

近年来,离子敏感场效应晶体管(ISFET)生物传感器因其灵敏度高、速度快、无标记、体积小、成本低等特点而受到了广泛关注,可应用于DNA、蛋白质、酶、细胞、离子等生物识别物的检测。ISFET生物传感器在金属氧化物半导体场效应晶体管(MOSFET)的基础上发展而来,通过溶液和传感层之间产生电荷转移,形成界面电位,从而改变FET的电流。综述了基于ISFET的生物传感器的工作原理,对器件类型进行了分类,分析了各种器件结构的特性,并列举了最新的应用进展,对未来实现高性能、微型化、可量产的ISFET生物传感器具有重要作用。     

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-gate metal oxide semiconductor (MOS) transistor is discussed using a device simulator. The simulation results predict that the nonself-aligned bottom-gate MOS transistor cannot be scaled into the deep submicron regions. A simple fully self-aligned bottom-gate (FSABG) metal oxide semiconductor field effect transistor (MOSFET) technology is then proposed and developed. A new technique for forming thermal oxide on poly-Si serving as the bottom-gate dielectric is also investigated. It is found that the quality of the oxide on the poly-Si recrystallized by the metal induced uni-lateral crystallization (MIUC) is much higher than that by the solid phase crystallization (SPC). Deep submicron fully self-aligned bottom-gate pMOS transistors are fabricated successfully using the proposed technology. The experimentally measured results indicate the device performances depend strongly on the channel-width, and get comparable to that of a single crystal MOSFET if the channel width is less than 0.5/spl mu/m. The effects of the channel width on the device performances are discussed. In addition, the experimental results also confirm that the proposed technology has a good control of the channel film thickness.     

Application of direct-tunneling gate oxides to high-performance CMOS

The characteristics of direct-tunneling gate oxide metal-oxide semiconductor field effect transistor (MOSFET)s are described. The effect of gate leakage current on MOSFET characteristics drops off as the gate length is reduced. Extremely good DC and AC performance has been realized using ultra-thin oxides down to 1.5 nm. Improved hot-carrier reliability and high oxide breakdown voltage have also been observed.     

伯克利短沟道绝缘栅场效应晶体管模型的研究进展

随着金属氧化物半导体(MOS)集成电路工艺的飞速发展,体硅金属氧化物半导体场效应晶体管(MOSFET)模型经历了从物理到经验,最后到半经验物理的转变.介绍了以阈值电压和反转电荷为建模基础的伯克利短沟道绝缘栅场效应晶体管模型(BSIM),以及该模型中阈值电压、饱和电流和电容的基本建模理论.回顾了近年来体硅MOSFET BSIM的研究进展,着重从各种模型的优缺点、建模机理和适用范围方面分析了4种最有代表性的BSIM,即BSIM3v3,BSIM4,BSIM5和BSIM6.从模型的发展历史可以看出模型是随着MOSFET尺寸的缩小而不断完善和发展的.最后,对体硅MOSFET的模型发展趋势进行了展望.     

Solution-processed organic–inorganic hybrid CMOS inverter exhibiting a high gain reaching 890

In this letter, we present a fabrication scheme and device performances of an organic–inorganic hybrid CMOS inverter employing a high-performance p-type organic semiconductor and an amorphous metal oxide layers. A deterioration of the oxide layer during device processing, which is often found in solution-processed semiconductor oxides, can be avoided by a one-shot solution-crystallization technique utilizing a polymer-blend. Both the p- and the n-type channels exhibited excellent transistor performances with high carrier mobilities and with precipitous turn-on behaviors near the gate voltages of 0 V, resulting in a successful demonstration of an ideal CMOS inverter operation with gain of 890. This result will update a potential excellence of organic–inorganic hybrid CMOS circuits in practical devices.     

基于高压IGBT暂态机理模型的分析与研究

随着绝缘栅双极性晶体管（IGBT）使用的电压等级越来越高,关于绝缘栅双极性晶体管（IGBT）开关暂态的研究显得尤为重要。在机理模型的基础上能细划分为MOSFET与BJT,即金属氧化层半导体场效晶体管与双极结型晶体管两个部分,对其进行建模,列举出模型参数提取方法。该模型可在Matlab中实现,把IGBT作为案例列出模型参数数值,分析比较高压开通暂态、关闭暂态与开关损耗仿真结果,以此检验机理模型对高压IGBT是否适用。     

Schottky‐Barrier‐Controllable Graphene Electrode to Boost Rectification in Organic Vertical P–N Junction Photodiodes

Monolayer graphene is used as an electrode to develop novel electronic device architectures that exploit the unique, atomically thin structure of the material with a low density of states at its charge neutrality point. For example, a single semiconductor layer stacked onto graphene can provide a semiconductor–electrode junction with a tunable injection barrier, which is the basis for a primitive transistor architecture known as the Schottky barrier field‐effect transistor. This work demonstrates the next level of complexity in a vertical graphene–semiconductor architecture. Specifically, an organic vertical p‐n junction (p‐type pentacene/n‐type N,N′‐dioctyl‐3,4,9,10‐perylenedicarboximide (PTCDI‐C₈)) on top of a graphene electrode constituting a novel gate‐tunable photodiode device structure is fabricated. The model device confirms that controlling the Schottky barrier height at the pentacene–graphene junction can (i) suppress the dark current density and (ii) enhance the photocurrent of the device, both of which are critical to improve the performance of a photodiode.     

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.     

Analytical Modeling of Quantum Mechanical Tunneling in Germanium Nano-MOSFETS

A simple analytical model has been developed to study quantum mechanical effects (QME)in a germanium substrate MOSFET (metal oxide semiconductor field effect transistor),which includes gate oxide tunneling considering the energy quantization effects in the substrate.Some alternate high dielectric constant materials to reduce the tunneling have also been studied.By comparing with the numerically reported results,the results match well with the existing reported work.     

A CMOS-integrated `ISFET-operational amplifier' chemical sensoremploying differential sensing

The ISFET (ion-sensitive field-effect transistor) pH sensor is first matched with a MOSFET at the differential input stage of a CMOS operational amplifier (called the ISFET-operational amplifier) to cancel out the temperature sensitivity. Then, the output of an ISFET-operational amplifier with a Ta₂O₅/SiO₂ gate (58-59 mV/pH) ISFET is differentially amplified against the output of another on-chip ISFET-operational amplifier with a SiO_x N_y/Si₃N₄/SiO₂ gate ISFET (18-20-mV/pH). An on-chip noble metal counterelectrode serves as the electrical contact to define the electric potential of the electrolyte. No external reference electrode is required. The difference measurement technique achieves (1) common-mode rejection of the solution potential, and (2) relaxation of the requirement that the on-chip reference electrode be ideal. The CMOS-compatible ISFET process is modified from a standard self-aligned polysilicon gate CMOS process with minimal process redesign. The standard CMOS sequence is unaltered until the contact windows are opened. The complete sensor has 40-43-mV/pH pH sensitivity and demonstrates common-mode rejection to ambient light and noise from the electrolyte     

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

Double Gate MOSFET Modeling Based on Adaptive Neuro‐Fuzzy Inference System for Nanoscale Circuit Simulation

As the conventional silicon metal‐oxide‐semiconductor field‐effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro‐fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics‐based models, like non‐equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.     

A resonant MOSFET gate driver with efficient energy recovery

High frequency pulse-width modulation (PWM) converters generally suffer from excessive gate drive loss. This paper presents a resonant gate drive circuit that features efficient energy recovery at both charging and discharging transitions. Following a brief introduction of metal oxide semiconductor field effect transistor (MOSFET) gate drive loss, this paper discusses the gate drive requirements for high frequency PWM applications and common shortcomings of existing resonant gate drive techniques. To overcome the apparent disparity, a new resonant MOSFET gate drive circuit is then presented. The new circuit produces low gate drive loss, fast switching speed, clamped gate voltages, immunity to false trigger and has no limitation on the duty cycle. Experimental results further verify its functionality.     

The permeable base transistor and its application to logic circuits

The permeable base transistor (PBT), which has been fabricated and operated as a microwave device, is described. Numerical solutions of Poisson's equation and the continuity equation show that this transistor could be used as a very high speed switch in a logic gate. It is predicted that with this device in an inverter gate having a fan out of one, a gate delay of 2 ps and a power-delay product of 0.1 fJ are possible. The unique feature of this transistor is the use of a metal grating embedded in the single-crystal semiconductor. The voltage on this grating controls the current between the grating fingers. By proper choice of carrier concentration and grating dimensions, enhancement and depletion mode devices can be made which allow simple gate designs similar to those of nMOS to be used. The lithographic and metal grating fabrication technologies are already well advanced and appear capable of producing PBT integrated circuits. The crystal embedding techniques for placing the metal inside the crystal are new and need further development. In the design of gates and circuits the embedded metal layers will provide the advantage of an interconnect layer inside the crystal, which reduces the number of layers required on the top of the semiconductor surface.