共查询到20条相似文献,搜索用时 31 毫秒
1.
Nakajima H. Yanagi S. Komiya K. Omura Y. 《Electron Devices, IEEE Transactions on》2002,49(10):1775-1782
This paper estimates the off-leakage current (I/sub off/) and drive current (I/sub on/) of various SOI MOSFETs by simulations based on the hydrodynamic-transport model; the band-to-band tunneling (BBT) effect at the drain is taken into consideration. Here, the simulations are done for SOI structures with a thick channel where the distinct quantization of energy is irrelevant to the present results. It is shown that merging hydrodynamic transport with the BBT effect is indispensable if realistic I/sub off/ estimates are to be achieved. It is shown that the symmetric double-gate SOI MOSFET does not always offer better drivability than other SOI MOSFETs, and that a single-gate SOI MOSFET with carefully selected parameters exhibits superior performance to double-gate SOI MOSFETs. It is also demonstrated that the quantum tunnel current is not significant, even in 20-nm channel SOI MOSFETs. The results suggest that we can still employ the conventional semi-classical method to estimate the off-leakage current of sub-100-nm channel low-power SOI MOSFETs. 相似文献
2.
A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI. 相似文献
3.
Zahra Arefinia 《Materials Science in Semiconductor Processing》2013,16(5):1240-1247
We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET. 相似文献
4.
Sub-50 nm P-channel FinFET 总被引:6,自引:0,他引:6
Xuejue Huang Wen-Chin Lee Kuo C. Hisamoto D. Leland Chang Kedzierski J. Anderson E. Takeuchi H. Yang-Kyu Choi Asano K. Subramanian V. Tsu-Jae King Bokor J. Chenming Hu 《Electron Devices, IEEE Transactions on》2001,48(5):880-886
High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an Idsat of 820 μA/μm at Vds=Vgs=1.2 V and T ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm 相似文献
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7.
Pei G. Kedzierski J. Oldiges P. Ieong M. Kan E.C.-C. 《Electron Devices, IEEE Transactions on》2002,49(8):1411-1419
Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplace's equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison. 相似文献
8.
A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model. 相似文献
9.
Semiconductor thickness effects in the double-gate SOI MOSFET 总被引:3,自引:0,他引:3
10.
Implementation and characterization of the double-gate MOSFET using lateral solid-phase epitaxy 总被引:1,自引:0,他引:1
In this paper, a simple high performance double-gate metal oxide semiconductor field effect transistor (MOSFET) using lateral solid-phase epitaxy (LSPE) is experimentally demonstrated and characterized. The thin channel of the double-gate MOSFET was obtained using the high quality LSPE crystallized layer. The fabricated double-gate MOSFET provides good current drive capability and steep subthreshold slope, and they are approximately 350 /spl mu/A//spl mu/m (@ V/sub ds/ = 2.5 V and V/sub gs/ - V/sub T/ = 2.5 V) and 78 mV/dec for the devices with 0.5 /spl mu/m channel length. Compared to the conventional single-gate transistor, the double-gate NMOSFET fabricated on the LSPE layer has better V/sub T/ roll-off characteristics, DIBL effect, and 1.72 times higher current drive. The peak effective electron mobility of the LSPE crystallized layer is approximately 382 cm/sup -2//V.s. 相似文献
11.
Shengdong Zhang Ruqi Han Xinnan Lin Xusheng Wu Mansun Chan 《Electron Device Letters, IEEE》2004,25(9):661-663
A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter. 相似文献
12.
Ernst T. Ritzenthaler R. Faynot O. Cristoloveanu S. 《Electron Devices, IEEE Transactions on》2007,54(6):1366-1375
13.
We introduce Silicon/indium arsenide (Si/InAs) source submicron-device structure in order to minimize the impact of floating body effect on both the drain breakdown voltage and single transistor latch in ultra thin SOI MOSFETs. The potential barrier of valence band between source and body reduces by applying the Indium Arsenide (InAs) layer at the source region. Therefore, we can improve the drain breakdown by suppressing the parasitic NPN bipolar device and the hole accumulation in the body. As confirmed by 2D simulation results, the proposed structure provides the excellent performance compared with a conventional SOI MOSFET thus improving the reliability of this structure in VLSI applications. 相似文献
14.
Sanjoy Deb N. Basanta Singh Debraj Das A.K. De 《International Journal of Electronics》2013,100(11):1465-1481
A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement. 相似文献
15.
《Electron Devices, IEEE Transactions on》2009,56(1):93-99
16.
In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET. 相似文献
17.
The two tightly coupled channels in independently driven double-gate (IDDG) MOSFET offer new opportunities in constructing mixed-signal circuit modules. Understanding of channel coupling in various bias and frequency regimes is imperative to conceptualize the circuit design and optimization. In Part I, we will investigate both quasi-static and nonquasi-static channel coupling in IDDG through capacitance simulation. The charge reshuffling between channels provides effective coupling at high frequency when source/drain (S/D) carriers cannot respond spontaneously to the applied gate signals, which opens up new high-frequency circuit possibilities beyond the S/D transit time set by the lithography limit. The bias and frequency regions that enhance channel coupling are identified. The transition frequency related to channel charge reshuffling is investigated for its dependence on device geometry. Operational principles and practical limitations are discussed. In Part II, we will present the circuit design examples based on the interchannel coupling. 相似文献
18.
《Electron Devices, IEEE Transactions on》2009,56(6):1284-1291
19.
Elimination of bipolar induced drain breakdown and singletransistor latch in submicron PD SOI MOSFET
For the first time, we report the combined application of a SiGe source and a delta-doped p+ region in a PD SOI MOSFET to minimize the impact of floating body effect on both the drain breakdown voltage and the single transistor latch. Our results demonstrate that the proposed SOI structure exhibits as large as 200% improvement in the breakdown voltage and is completely immune to single transistor latch when compared to the conventional SOI MOSFET thus improving the reliability of these structures in VLSI applications 相似文献
20.
Transient charge pumping as an efficient technique to measure low light intensity with PD SOI MOSFET
In this paper, we present a new method to measure light intensity in a floating body partially depleted SOI MOSFET. The photo-generated charge density in the MOSFET is converted into a charge pumping frequency needed to maintain the drain current at a constant value. This new approach contrasts with conventional techniques that rely on an accurate drain current evaluation. According to our measurements, flux densities as low as 2 mW/m2 were obtained using a regular SOI MOSFET, thus confirming the potentials of this approach. 相似文献