Pseudorandom signal sampler for relaxed design of multistandard radio receiver

This paper proposes a novel software defined radio (SDR) receiver design using non-uniform sampling (NUS) technique implemented by original design of a pseudorandom signal sampler (PSS) circuit for controlling data conversion to relax multistandard receiver circuit constraints. The proposed and designed NUS-based SDR receiver allows spectral alias suppression at integer multiples of sampling frequency offering the advantages of relaxing anti-aliasing filter (AAF), reducing the analog-to-digital converter (ADC) dynamic power consumption and the automatic gain control (AGC) range as well. The PSS circuit, generating pseudorandom clock signal, with enough time-quantization accuracy, was designed. The PSS is implemented in 65-nm digital CMOS technology and occupies 470 (μm)². It features up to 200 MHz “mean clock” for 3.2 GHz main clock while drawing 242 μA for 1.2 V supply. Mixed experimental/simulation tests, of designed NUS-based SDR receiver, revealed a confirmation of alias-free performances and the achievement of a 72 dB (12-bit ADC) dynamic range after signal reconstruction.     

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC’s specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This circuit is designed in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR at 2.112 GHz sampling rate with 36 mW power consumption and the effective figure of merit value is 0.24 pJ/step.     

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.     

A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth

An integrated low-noise amplifier, mixer, bandpass /spl Delta//spl Sigma/ analog-to-digital converter (ADC), decimation filter, and two synthesizers implement a general-purpose back-end for a narrow-band superheterodyne receiver. The /spl Delta//spl Sigma/ ADC is merged with the mixer and combines LC, active-RC, and switched-capacitor resonators to achieve low noise and robust operation with low power consumption. A variable full-scale feature adds an automatic-gain-control capability to the ADC while saving power and minimizing noise at low signal levels.     

一种任意抽取数字下变频器的设计

数字下变频（DDc）技术作为连接前端模数转换器件（ADC）与后端通用数字信号处理器件之间的纽带,在雷达信号处理中占据了核心地位。针对雷达不同模式下抽取率不同的情况,本文提出了一种任意抽取数字下变频芯片的设计,实现了不同抽取率时的乘法器资源复用,节约了乘法器资源,降低了系统功耗和系统的复杂度。该数字下变频芯片采用SMICO．13μm工艺进行综合仿真,综合结果满足指标要求。     

A reconfigurable low-pass/high-pass \varDelta \varSigma ADC suited for a zero-IF/low-IF receiver

This paper presents the design of a reconfigurable delta sigma analog to digital converter. Its main degree of freedom is the choice of the noise shaping between low-pass and high-pass. Thanks to this reconfiguration parameter, the converter takes full advantage of both noise shapings and employs the most suited architecture depending on the received standard. Moreover, the low-pass/high-pass reconfiguration makes the analog-to-digital converter compliant for both the low-IF and the zero-IF receiver architectures. The paper also presents a novel reconfigurable dynamic element matching technique which efficiently addresses the digital to analog converter mismatch for both the high-pass and the low-pass delta sigma modulators. The sampling frequency and the quantizer number of bits are likewise adjustable. A GSM/UMTS compliant delta sigma analog to digital converter including reconfigurable decimator has been designed in a 1.2 V 65 nm CMOS process. The high-pass modulator is employed in a low-IF receiver for the GSM mode to profit from its robustness against offset and 1/f noise. For the UMTS mode, the low-pass modulator is employed in a zero-IF receiver because of its lower sensitivity to clock jitter.     

Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver

A low power ultra-wideband impulse radio (UWB-IR) receiver was developed in 0.18-mum CMOS. All circuits of the receiver AFE operate intermittently with a sampling clock of an analog-digital converter (ADC). The sampling rate of the ADC is equal to the pulse repetition frequency of the received signals. Power consumption of the receiver AFE is reduced by 60% using a developed intermittent operation scheme without degrading of receiver sensitivity. As a result, the power consumption of the receiver AFE is 38 mW. The receiver has a data rate of 258 kb/s over a distance of 52 m and of 10.7 Mb/s over a distance of 14 m.     

RF Band‐Pass Sampling Frontend for Multiband Access CR/SDR Receiver

Radio frequency (RF) subsampling can be used by radio receivers to directly down‐convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog‐to‐digital converter (ADC) as near the antenna as possible. Based on this, a band‐pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second‐order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second‐order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second‐order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.     

基于软件无线电的直接扩频序列接收机新方案

在低信噪比的低压电力线通信环境中,使用传统的扩频解调方法,不易提取同步载波。针对这一问题,提出一种基于软件无线电结构的直接扩频序列（Dsss）接收机方案。该方案以带通采样定理为依据,结合A／D转换器和数字低通滤波器,无需提取同步栽波即可完成已调信号的解调,并在基带完成信号的解扩。通过理论和仿真证明,该方案开销低,抗噪性能强,适合在恶劣的通信环境中使用。     

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.     

12位Sigma-Delta模数转换器的降采样滤波器设计

一种由SNR（信噪比）驱动的滤波器设计,用于12位Sigma-Delta模数转换器。Sigma-Delta模数转换器包括Sigma-Delta调制器和降采样滤波器两部分,首先用Sigma-Delta调制器对信号进行过采样率量化,然后通过降采样滤波器进行数字信号处理,将信号还原到原始采样率并去除量化噪声。和传统的模数转换器相比,Sigma-Delta模数转换器具有采样率高、精度高、面积小等优点。Sigma-Delta模数转换器的滤波器设计有降采样率和滤波性能两个指标要求,该设计方法由SNR驱动并采用了两种滤波器方案,设计结果在MATLAB里进行了仿真,其SNR大于74 dB,达到12位Sigma-Delta模数转换器的要求。     

SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications

A low-power phase-shift keying demodulator integrated circuit (IC) has been implemented using silicon-on-insulator CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit analog-to-digital converter (ADC) at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at ultra-high-frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit ADC is below 1 mW for data rates up to 100 Kbps     

An 8-bit, 10 kHz, 5.1 μW, 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities

An 5.1 μW, 1.8 V, 8-bit, successive approximation (SAR) analog-to-digital converter (ADC) using 10 kHz clock was designed and fabricated in a 0.18 μm CMOS technology for passive UHF radio frequency identification (RFID) applications. The ADC utilises a resistive digital to analog converter (DAC). The ADC can operate with low power consumption. The proposed comparator with cascode active load can offer large gain and can operate at a low supply voltage. The measured total power consumption is 5.1 μW at a 10 kHz input clock with a 1.8 V single supply, and 0.5 μW with 970 mV supply.     

ADC的动态性能对软件无线电接收机性能的影响

软件无线电技术在商用和军用无线电通信领域越来越显示出其强大的吸引力,而ADC是软件无线电的关键技术。概括了A/D转换器在无线电接收机中的应用,分析了其动态性能中互调失真、SFDR(无杂散动态范围)、孔径抖动对接收机性能的影响。最后以AD公司的AD9445为例,进行了仿真。     

软件无线电宽带高中频采样的A/D特性分析

从软件无线电对宽带中频模数变换器(ADC)的要求出发,首先提出了一种以欠采样技术为基础的方案,并对宽带信号的采样率进行了计算;然后详细分析了地面反弹等因素对ADC器件性能的影响,给出了具体的分析结果,最后介绍了指标选取时需考虑的因素。本文的分析和结论对宽带中频采样的设计和器件选取有一定指导意义。     

中频采样全数字接收机的设计与实现

根据侦察接收机的需要,基于软件无线电理论提出了一种中频采样全数字接收机的设计方案,对其中的带通采样单元、数字下变频单元和解调单元进行了分析。数字下变频采用高效滤波抽取方案,对CIC、HB和FIR滤波器的设计进行了详细介绍。最后在基于FPGA的CPCI接口信号处理平台上进行了实现,完成了多种信号的解调处理,系统具有高度的灵活性和可扩展空间。     

Theoretical performance analysis of radio frequency fingerprinting under receiver distortions

Radio frequency fingerprinting (RFF) is used to uniquely identify individual emitters by exploiting the radio frequency characteristics, which are originated from transmitter imperfections. The theoretical performance is analyzed to evaluate the feasibility of RFF with channel noise and receiver imperfections. The distortions from oscillators and analog‐to‐digital converter (ADC) are considered, and a RFF signal model describing the discrepancies of transmitter imperfections, channel noise, and receiver distortions are constructed. A likelihood ratio test algorithm for RFF is proposed to analyze the theoretical performance. The upper and lower bound of theoretic performance is derived through the analysis of the likelihood ratio test statistic, which enlightens how to design a “just enough” receiver to meet the demands of RFF. The simulation results are in agreement with the theoretical evaluation. Copyright © 2013 John Wiley & Sons, Ltd.     

一种基于循环ADC结构的可配置Pipeline ADC系统设计

通过对Pipeline ADC系统的精度和工作频率可配置原理进行探讨,提出了一种新颖的精度和工作频率可配置Pipeline ADC设计理念,并对系统和子模块进行了设计.可配置的Pipeline ADC的精度可配置在8/10/12bit,工作频率可配置在10/20/40MHz.考虑电路中的增益有限性等因素的影响,使用Matlab对系统建模并仿真.系统仿真结果表明,可配置的Pipe-lineADC系统能够达到满意的SNR、有效位数等性能指标要求.     

一种4bit相位量化ADC电路分析

针对数字射频存储器(DRFM)量化方式的差异、优势和不同的应用范围,介绍相位量化模数转换器(ADC)的系统架构,提出相位量化ADC主要电路模块的一种实现方案,比较了该方案与传统方式的区别,并基于0.13μm互补型金属氧化物半导体场效应晶体管(CMOS)工艺模型进行仿真,仿真结果表明该芯片可在1.2 GHz时钟速率下完成采样、量化,瞬时带宽可达250 MHz,具有+0.2 LSB的相位精度。     

带通采样在数字多通道中频接收机中的应用

论述了带通信号采样定理,在对带通采样后的频谱结构做了详细分析的基础上,提出中频频率、采样频率的选取方法。将带通欠采样技术运用到软件无线电中频接收机设计中,并给出了带通采样定理在的不同条件下Matlab仿真的结果,验证了带通采样技术在宽带数字多通道、多速率、多模式软件无线电中频接收机设计中的可行性和实用性,在工程应用中具有较大的参考意义。